EPM5192AJC84-20 vs EPM5192AJM84-20 比較
詳細並排比較 EPM5192AJC84-20 由 Altera 與 EPM5192AJM84-20 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EPM5192AJC84-20 - 192-Macrocell UV PLD, 33ns, 84-Pin J-Lead | Altera
EPM5192AJC84-20 Obsolete
規格比較
| 參數 | EPM5192AJC84-20 | EPM5192AJM84-20 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 | — |
| Device Type | UV-erasable/OTP Complex PLD (CPLD) | CMOS UV-Erasable/OTP Complex PLD |
| Macrocells | 192 | 192 |
| Propagation Delay (tpd) | 33 ns (speed grade -20) | — |
| 最大時脈頻率 | 66.7 MHz | 66.7 MHz |
| Supply Voltage (Vcc) | 4.75 V to 5.25 V | — |
| Dedicated Inputs | 7 | 7 |
| User I/O Lines | 64 | — |
| Process Technology | CMOS, UV-erasable EEPROM | CMOS EPROM (UV-erasable) |
| 封裝 | 84-pin PLCC J-Lead (WQCCJ, J84) | 84-pin CQFP (S-CQCC-J84, J-lead) |
| Operating Temperature Grade | Commercial | — |
| 安裝類型 | Surface Mount (J-Lead) | — |
| MSL 等級 | [DATA_NEEDED: MSL level] | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: rohs status] |
| Programming Tool | Altera MAX+PLUS II / Quartus (legacy) | — |
| Lead-Free / Halogen-Free | [DATA_NEEDED: lead-free status] | — |
| Manufacturer | — | Altera (now Intel) |
| Series | — | MAX 5000 (EPM5192) |
| Logic Array Blocks (LABs) | — | 12 |
| User I/O Pins | — | 64 |
| Programmable Interconnect | — | PIA (Programmable Interconnect Array) |
| Propagation Delay (tPD) | — | 33 ns (speed grade -20) |
| Terminal Form | — | J-Bend |
| Temperature Grade | — | MILITARY |
| Erasure Method | — | UV (quartz-windowed CQFP) or OTP |