EPM5192GI-1 vs EPM5192LI-1 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192GI-1 sa pamamagitan ng Altera at EPM5192LI-1 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5192GI-1 | EPM5192LI-1 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Family | MAX 5000 | MAX 5000 |
| Device Type | Complex Programmable Logic Device (CPLD) | EPLD (UV-Erasable/OTP Complex PLD) |
| Architecture | PAL-type, UV-erasable CMOS | EEPROM/EPROM-based, non-volatile, instant-on |
| Macrocells | 192 | 192 |
| User I/O Pins | 64 | [DATA_NEEDED: user I/O count for JLCC variant] |
| Dedicated Inputs | 7 | — |
| Logic Array Blocks (LABs) | 12 | — |
| Propagation Delay (tPD) | 25 ns | [DATA_NEEDED: tPD in ns at -1 grade] |
| Maximum Clock Frequency (fMAX) | 62.5 MHz | — |
| Supply Voltage (VCC) | 5.0 V | — |
| Temperature na Operasyon | -40C to +85C (Industrial) | [DATA_NEEDED: industrial vs military range] |
| Packhaging | 84-pin PGA (Pin Grid Array), windowed ceramic | — |
| Configuration Memory | UV-EPROM (windowed ceramic PGA) | — |
| Process Technology | CMOS | CMOS EPROM, UV-erasable |
| Tindminan RoHS | unknown (legacy UV-windowed package) | [DATA_NEEDED: RoHS status of ceramic LI variant] |
| Usable Gates | — | 3,750 |
| Maximum Toggle Frequency | — | 40 MHz |
| Volte ng Pagbibigay | — | 5 V |
| Package Type | — | JLCC (windowed, ceramic, UV-erasable) |
| Speed Grade | — | -1 |
| Bilang ng Pin | — | [DATA_NEEDED: pin count of LI package] |
| Uri ng Pagpapasok | — | Surface Mount (JLCC with J-leads) |
| Level ng MSL | — | [DATA_NEEDED: MSL level] |
| Lead Free | — | [DATA_NEEDED: lead-free] |
| Programmable Interconnect | — | Programmable Interconnect Array (PIA) |