EPM5192JC-ES vs EPM5192JC-1 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192JC-ES sa pamamagitan ng Intel at EPM5192JC-1 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5192JC-ES EPM5192JC-1
Brand Intel Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Device Family MAX 5000 —
Device Type CPLD (EPLD) CPLD - Complex Programmable Logic Device
Macrocells 192 192
Logic Array Blocks (LABs) 12 —
Interconnect Programmable Interconnect Array (PIA) —
Configuration Memory EPROM (UV-erasable, one-time programmable for JC-ES) UV-EPROM (erasable under UV lamp)
Packhaging 84-pin PLCC (J-lead, CQCC, JEDEC S-CQCC-J84) —
Uri ng Pagpapasok Surface Mount —
Technology CMOS CMOS, UV-Erasable / OTP
Programming Altera MAX+PLUS II or compatible programmer —
Temperature na Operasyon [DATA_NEEDED: operating temperature range for ES grade] 0 C to +70 C (commercial)
Volte ng Pagbibigay [DATA_NEEDED: VCC nominal] —
User I/O Pins [DATA_NEEDED: user I/O count for JC-ES in PLCC-84] 84
Tindminan RoHS [DATA_NEEDED: RoHS compliance] —
Lead-Free [DATA_NEEDED: lead-free status] —
Level ng MSL [DATA_NEEDED: MSL rating] —
Note Datasheet source: Altera MAX 5000 family document, 52 pages —
Family — MAX 5000
Usable Gates — 3750
Propagation Delay (tPD) — 40 ns (speed grade -1)
Maximum Internal Frequency (fMAX) — 62.5 MHz
Supply Voltage (VCC) — 4.75 V to 5.25 V
Package Type — 84-pin Ceramic Quad Flat Pack (CQFP), windowed
JEDEC Package Code — S-CQCC-J84
Programming Interface — Altera MAX programming interface (parallel, pre-JTAG for this family)
Process — CMOS EPROM
I/O Standard — TTL/CMOS 5 V compatible

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