EPM5192JC vs EPM5192JC-2 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192JC sa pamamagitan ng Intel at EPM5192JC-2 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5192JC | EPM5192JC-2 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Product Type | CPLD (Complex Programmable Logic Device) | UV-erasable Programmable Logic Device (PLD) |
| Series | EPM5192 (Classic / MAX-class) | — |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | 12 |
| Interconnect Architecture | Programmable Interconnect Array (PIA) | — |
| Process Technology | CMOS EPROM (UV-erasable) | CMOS |
| Packhaging | 68-pin PLCC (JC) windowed ceramic | 84-pin CQCC (Ceramic Quad Flat Pack, J-lead, windowed) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Programming Method | UV-erase + EPROM programmer | UV-erase / EPROM |
| Non-Volatile Configuration | Yes (EPROM cell array) | — |
| Logic Family | Classic CPLD (EPM5xxx series) | — |
| Temperature na Operasyon | [DATA_NEEDED: commercial / industrial / military grade] | — |
| Volte ng Pagbibigay | [DATA_NEEDED: VCC nominal] | — |
| Propagation Delay | [DATA_NEEDED: tpd spec by speed grade] | — |
| Tindminan RoHS | [DATA_NEEDED: original Altera marking not RoHS] | [DATA_NEEDED: RoHS compliance] |
| Device Family | — | MAX 5000 |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| User I/O Pins | — | 64 |
| Dedicated Inputs | — | 7 |
| External Clock Inputs | — | 1 |
| Propagation Delay (tPD) | — | 45 ns |
| Maksimum na Taktiko ng Oras | — | 40 MHz |
| Number of Terminals | — | 84 |
| Hanay ng Temperature na Operasyon | — | [DATA_NEEDED: operating temperature range] |