EPM5192JC vs EPM5192JC-2 比較
詳細並排比較 EPM5192JC 由 Intel 與 EPM5192JC-2 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5192JC | EPM5192JC-2 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Product Type | CPLD (Complex Programmable Logic Device) | UV-erasable Programmable Logic Device (PLD) |
| Series | EPM5192 (Classic / MAX-class) | — |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | 12 |
| Interconnect Architecture | Programmable Interconnect Array (PIA) | — |
| Process Technology | CMOS EPROM (UV-erasable) | CMOS |
| 封裝 | 68-pin PLCC (JC) windowed ceramic | 84-pin CQCC (Ceramic Quad Flat Pack, J-lead, windowed) |
| 安裝類型 | Surface Mount | Surface Mount |
| Programming Method | UV-erase + EPROM programmer | UV-erase / EPROM |
| Non-Volatile Configuration | Yes (EPROM cell array) | — |
| Logic Family | Classic CPLD (EPM5xxx series) | — |
| 工作溫度 | [DATA_NEEDED: commercial / industrial / military grade] | — |
| 供應電壓 | [DATA_NEEDED: VCC nominal] | — |
| Propagation Delay | [DATA_NEEDED: tpd spec by speed grade] | — |
| RoHS 狀態 | [DATA_NEEDED: original Altera marking not RoHS] | [DATA_NEEDED: RoHS compliance] |
| Device Family | — | MAX 5000 |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| User I/O Pins | — | 64 |
| Dedicated Inputs | — | 7 |
| External Clock Inputs | — | 1 |
| Propagation Delay (tPD) | — | 45 ns |
| 最大時脈頻率 | — | 40 MHz |
| Number of Terminals | — | 84 |
| 工作溫度範圍 | — | [DATA_NEEDED: operating temperature range] |