EPM5192JI-1 vs EPM5192LI-1 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192JI-1 sa pamamagitan ng Intel at EPM5192LI-1 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5192JI-1 EPM5192LI-1
Brand Intel Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete NRND
Family MAX 5000 MAX 5000
Device Type CMOS UV-Erasable Programmable Logic Device (PLD / EPLD) EPLD (UV-Erasable/OTP Complex PLD)
Macrocells 192 192
Logic Array Blocks (LABs) 12 —
User I/O Pins 64 [DATA_NEEDED: user I/O count for JLCC variant]
Dedicated Inputs 7 —
Propagation Delay (tPD) 55 ns [DATA_NEEDED: tPD in ns at -1 grade]
Supply Voltage (VCC) 4.5 V to 5.5 V (nominal 5 V) —
Process Technology CMOS EPROM CMOS EPROM, UV-erasable
Packhaging 84-pin JLCC (Windowed ceramic J-lead) —
Temperature na Operasyon Industrial, -40 C to +85 C [DATA_NEEDED: industrial vs military range]
Configuration Memory UV-erasable EPROM —
Programming Method External EPROM programmer (via programming hardware) —
Tindminan RoHS [DATA_NEEDED: RoHS compliance] [DATA_NEEDED: RoHS status of ceramic LI variant]
Speed Grade -1 (slowest grade in EPM5192 family) -1
Logic Element per Macrocell 1 D flip-flop + AND/OR array —
Usable Gates — 3,750
Maximum Toggle Frequency — 40 MHz
Volte ng Pagbibigay — 5 V
Package Type — JLCC (windowed, ceramic, UV-erasable)
Bilang ng Pin — [DATA_NEEDED: pin count of LI package]
Uri ng Pagpapasok — Surface Mount (JLCC with J-leads)
Level ng MSL — [DATA_NEEDED: MSL level]
Lead Free — [DATA_NEEDED: lead-free]
Programmable Interconnect — Programmable Interconnect Array (PIA)
Architecture — EEPROM/EPROM-based, non-volatile, instant-on

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