EPM5192JI-2 vs EPM5192JI Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192JI-2 sa pamamagitan ng Altera at EPM5192JI sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5192JI-2 | EPM5192JI |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (Erasable Programmable Logic Device) | EPLD (UV-erasable CMOS Programmable Logic Device) |
| Macrocells | 192 | 192 |
| Usable Gates | 5000 | — |
| Dedicated Inputs | 12 | 7 |
| Flip-Flops | 192 | — |
| Speed Grade | -2 | — |
| Packhaging | JLCC-68 (J-Lead Ceramic) | 84-pin PLCC (windowed, J-suffix ceramic) |
| Temperature na Operasyon | 0C to +70C (commercial) | -40 C to +125 C (industrial, I-suffix) |
| Programming Technology | UV-Erasable EPROM | — |
| Architecture | Sum-of-products with Programmable Interconnect Array (PIA) | — |
| Volte ng Pagbibigay | 5 V (typical) | 4.75 V to 5.25 V (nominal 5 V) |
| Process Technology | CMOS EPROM | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount (PLCC socket recommended for UV erasure) |
| Tindminan RoHS | Non-compliant (ceramic JLCC, contains lead) | [DATA_NEEDED: RoHS status - pre-2010 part, likely non-compliant] |
| Katayuan ng Lifecycle | Obsolete (legacy Altera MAX 5000 family) | — |
| Logic Array Blocks (LABs) | — | 12 |
| User I/O Pins | — | 64 |
| Propagation Delay (tpd) | — | 55 ns |
| Technology | — | CMOS EPROM, UV-erasable |
| Programming Method | — | Altera MAX 5000 programming algorithm (device programmer) |
| Erasure Method | — | UV exposure through windowed package |