EPM5192JI-2 vs EPM5192JI 比較
詳細並排比較 EPM5192JI-2 由 Altera 與 EPM5192JI 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5192JI-2 | EPM5192JI |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (Erasable Programmable Logic Device) | EPLD (UV-erasable CMOS Programmable Logic Device) |
| Macrocells | 192 | 192 |
| Usable Gates | 5000 | — |
| Dedicated Inputs | 12 | 7 |
| Flip-Flops | 192 | — |
| Speed Grade | -2 | — |
| 封裝 | JLCC-68 (J-Lead Ceramic) | 84-pin PLCC (windowed, J-suffix ceramic) |
| 工作溫度 | 0C to +70C (commercial) | -40 C to +125 C (industrial, I-suffix) |
| Programming Technology | UV-Erasable EPROM | — |
| Architecture | Sum-of-products with Programmable Interconnect Array (PIA) | — |
| 供應電壓 | 5 V (typical) | 4.75 V to 5.25 V (nominal 5 V) |
| Process Technology | CMOS EPROM | — |
| 安裝類型 | Surface Mount | Surface Mount (PLCC socket recommended for UV erasure) |
| RoHS 狀態 | Non-compliant (ceramic JLCC, contains lead) | [DATA_NEEDED: RoHS status - pre-2010 part, likely non-compliant] |
| 生命週期狀態 | Obsolete (legacy Altera MAX 5000 family) | — |
| Logic Array Blocks (LABs) | — | 12 |
| User I/O Pins | — | 64 |
| Propagation Delay (tpd) | — | 55 ns |
| Technology | — | CMOS EPROM, UV-erasable |
| Programming Method | — | Altera MAX 5000 programming algorithm (device programmer) |
| Erasure Method | — | UV exposure through windowed package |