EPM5192LC84 vs EPM5192LC84-2 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192LC84 sa pamamagitan ng Altera at EPM5192LC84-2 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5192LC84 | EPM5192LC84-2 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Product Type | Complex Programmable Logic Device (CPLD) | — |
| Family | MAX 5000 | MAX 5000 |
| Macrocells (Logic Cells) | 192 | — |
| Propagation Delay (tPD) | 55 ns | — |
| Process Technology | CMOS | — |
| Programmability | OTP / UV-Erasable | — |
| Packhaging | LCC-84 (PQCC84, MS-018) | 84-pin PLCC (LC) |
| Bilang ng Pin | 84 | — |
| Uri ng Pagpapasok | Surface Mount (Socket-compatible) | Surface Mount |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | Commercial (0C to +70C) |
| Volte ng Pagbibigay | [DATA_NEEDED: VCC range] | 5 V (TTL-compatible I/O) |
| User I/O | [DATA_NEEDED: max user I/O count] | — |
| Configuration Memory | EPROM / UV-Erasable | — |
| Programming Interface | JTAG / Altera legacy (MAX+PLUS II baseline) | — |
| Tindminan RoHS | unknown | Non-compliant (SnPb lead finish typical for this vintage) |
| Level ng MSL | [DATA_NEEDED: MSL rating] | — |
| Device Type | — | EPLD (UV-Erasable / OTP Complex PLD) |
| Macrocells | — | 192 |
| Speed Grade | — | -2 |
| Technology | — | CMOS, UV-erasable / OTP |
| Logic Elements | — | AND-OR array with macrocell flip-flops |
| Programming Method | — | Altera legacy programmer (JEDEC bitstream) |
| Katayuan ng Lifecycle | — | Obsolete (last Altera MAX 5000 production) |
| JTAG Support | — | Vendor-specific programming interface (pre-IEEE 1532) |
| I/O Standard | — | TTL, 5V CMOS-compatible |