EPM5192LC84 vs EPM5192LC84-2 比較
詳細並排比較 EPM5192LC84 由 Altera 與 EPM5192LC84-2 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5192LC84 | EPM5192LC84-2 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Product Type | Complex Programmable Logic Device (CPLD) | — |
| Family | MAX 5000 | MAX 5000 |
| Macrocells (Logic Cells) | 192 | — |
| Propagation Delay (tPD) | 55 ns | — |
| Process Technology | CMOS | — |
| Programmability | OTP / UV-Erasable | — |
| 封裝 | LCC-84 (PQCC84, MS-018) | 84-pin PLCC (LC) |
| 腳位數 | 84 | — |
| 安裝類型 | Surface Mount (Socket-compatible) | Surface Mount |
| 工作溫度 | [DATA_NEEDED: operating temperature range] | Commercial (0C to +70C) |
| 供應電壓 | [DATA_NEEDED: VCC range] | 5 V (TTL-compatible I/O) |
| User I/O | [DATA_NEEDED: max user I/O count] | — |
| Configuration Memory | EPROM / UV-Erasable | — |
| Programming Interface | JTAG / Altera legacy (MAX+PLUS II baseline) | — |
| RoHS 狀態 | unknown | Non-compliant (SnPb lead finish typical for this vintage) |
| MSL 等級 | [DATA_NEEDED: MSL rating] | — |
| Device Type | — | EPLD (UV-Erasable / OTP Complex PLD) |
| Macrocells | — | 192 |
| Speed Grade | — | -2 |
| Technology | — | CMOS, UV-erasable / OTP |
| Logic Elements | — | AND-OR array with macrocell flip-flops |
| Programming Method | — | Altera legacy programmer (JEDEC bitstream) |
| 生命週期狀態 | — | Obsolete (last Altera MAX 5000 production) |
| JTAG Support | — | Vendor-specific programming interface (pre-IEEE 1532) |
| I/O Standard | — | TTL, 5V CMOS-compatible |