EPM5192LI84 vs EPM5192LC84 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192LI84 sa pamamagitan ng Altera at EPM5192LC84 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5192LI84 | EPM5192LC84 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Device Family | MAX 5000 | — |
| Product Type | UV-Erasable/OTP Complex PLD (CPLD) | Complex Programmable Logic Device (CPLD) |
| Usable Gates | 3,750 gates | — |
| Macro Cells | 192 | — |
| Maximum Toggle Frequency | 40 MHz | — |
| Pin-to-Pin Delay (tPD) | 25 ns | — |
| Supply Voltage (VCC) | 5 V (single supply) | — |
| User I/O Pins | 64 (max) | — |
| Hanay ng Temperature na Operasyon | -40 °C to +85 °C (industrial) | — |
| Package Type | 84-pin PLCC (J-lead, package code J84/QCCJ) | — |
| Uri ng Pagpapasok | Surface Mount (socket-compatible) | Surface Mount (Socket-compatible) |
| Configuration Memory | OTP / UV-erasable EPROM | EPROM / UV-Erasable |
| Programming Method | Stand-alone programmer (no JTAG on LI84 OTP variant) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | unknown |
| Logic Compatibility | TTL-compatible I/O | — |
| Family | — | MAX 5000 |
| Macrocells (Logic Cells) | — | 192 |
| Propagation Delay (tPD) | — | 55 ns |
| Process Technology | — | CMOS |
| Programmability | — | OTP / UV-Erasable |
| Packhaging | — | LCC-84 (PQCC84, MS-018) |
| Bilang ng Pin | — | 84 |
| Temperature na Operasyon | — | [DATA_NEEDED: operating temperature range] |
| Volte ng Pagbibigay | — | [DATA_NEEDED: VCC range] |
| User I/O | — | [DATA_NEEDED: max user I/O count] |
| Programming Interface | — | JTAG / Altera legacy (MAX+PLUS II baseline) |
| Level ng MSL | — | [DATA_NEEDED: MSL rating] |