EPM5192LI84 vs EPM5192LI-1 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192LI84 sa pamamagitan ng Altera at EPM5192LI-1 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5192LI84 EPM5192LI-1
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete NRND
Device Family MAX 5000 —
Product Type UV-Erasable/OTP Complex PLD (CPLD) —
Usable Gates 3,750 gates 3,750
Macro Cells 192 —
Maximum Toggle Frequency 40 MHz 40 MHz
Pin-to-Pin Delay (tPD) 25 ns —
Supply Voltage (VCC) 5 V (single supply) —
User I/O Pins 64 (max) [DATA_NEEDED: user I/O count for JLCC variant]
Hanay ng Temperature na Operasyon -40 °C to +85 °C (industrial) —
Package Type 84-pin PLCC (J-lead, package code J84/QCCJ) JLCC (windowed, ceramic, UV-erasable)
Uri ng Pagpapasok Surface Mount (socket-compatible) Surface Mount (JLCC with J-leads)
Configuration Memory OTP / UV-erasable EPROM —
Programming Method Stand-alone programmer (no JTAG on LI84 OTP variant) —
Tindminan RoHS [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS status of ceramic LI variant]
Logic Compatibility TTL-compatible I/O —
Family — MAX 5000
Device Type — EPLD (UV-Erasable/OTP Complex PLD)
Macrocells — 192
Volte ng Pagbibigay — 5 V
Propagation Delay (tPD) — [DATA_NEEDED: tPD in ns at -1 grade]
Process Technology — CMOS EPROM, UV-erasable
Speed Grade — -1
Temperature na Operasyon — [DATA_NEEDED: industrial vs military range]
Bilang ng Pin — [DATA_NEEDED: pin count of LI package]
Level ng MSL — [DATA_NEEDED: MSL level]
Lead Free — [DATA_NEEDED: lead-free]
Programmable Interconnect — Programmable Interconnect Array (PIA)
Architecture — EEPROM/EPROM-based, non-volatile, instant-on

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