EPM5192LI84 vs EPM5192LI-2 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192LI84 sa pamamagitan ng Altera at EPM5192LI-2 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5192LI84 | EPM5192LI-2 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Device Family | MAX 5000 | — |
| Product Type | UV-Erasable/OTP Complex PLD (CPLD) | — |
| Usable Gates | 3,750 gates | — |
| Macro Cells | 192 | — |
| Maximum Toggle Frequency | 40 MHz | — |
| Pin-to-Pin Delay (tPD) | 25 ns | — |
| Supply Voltage (VCC) | 5 V (single supply) | — |
| User I/O Pins | 64 (max) | — |
| Hanay ng Temperature na Operasyon | -40 °C to +85 °C (industrial) | — |
| Package Type | 84-pin PLCC (J-lead, package code J84/QCCJ) | — |
| Uri ng Pagpapasok | Surface Mount (socket-compatible) | Surface Mount |
| Configuration Memory | OTP / UV-erasable EPROM | — |
| Programming Method | Stand-alone programmer (no JTAG on LI84 OTP variant) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Logic Compatibility | TTL-compatible I/O | — |
| Family | — | MAX 5000 |
| Device Type | — | EPLD (Erasable/OTP Complex PLD) |
| Macrocells | — | 192 |
| Logic Array Blocks (LABs) | — | 12 |
| User I/O | — | 64 |
| Total Inputs | — | 72 (7 dedicated + 64 I/O) |
| Propagation Delay (tpd) | — | 55 ns (max) |
| Maximum Internal Frequency | — | 100 MHz |
| Volte ng Pagbibigay | — | 4.5 V to 5.5 V |
| Temperature na Operasyon | — | -40 C to +85 C (industrial) |
| Typical Power Dissipation | — | 600 mW at 5 V / 25 C |
| Technology | — | CMOS, UV-erasable / OTP |
| Packhaging | — | 84-pin PLCC (J-lead), JEDEC S-PQCC-J84 |
| Design Toolchain | — | Altera MAX+plus II |