EPM5192LI84 vs EPM5192LI-2 比較
詳細並排比較 EPM5192LI84 由 Altera 與 EPM5192LI-2 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5192LI84 | EPM5192LI-2 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Device Family | MAX 5000 | — |
| Product Type | UV-Erasable/OTP Complex PLD (CPLD) | — |
| Usable Gates | 3,750 gates | — |
| Macro Cells | 192 | — |
| Maximum Toggle Frequency | 40 MHz | — |
| Pin-to-Pin Delay (tPD) | 25 ns | — |
| Supply Voltage (VCC) | 5 V (single supply) | — |
| User I/O Pins | 64 (max) | — |
| 工作溫度範圍 | -40 °C to +85 °C (industrial) | — |
| Package Type | 84-pin PLCC (J-lead, package code J84/QCCJ) | — |
| 安裝類型 | Surface Mount (socket-compatible) | Surface Mount |
| Configuration Memory | OTP / UV-erasable EPROM | — |
| Programming Method | Stand-alone programmer (no JTAG on LI84 OTP variant) | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Logic Compatibility | TTL-compatible I/O | — |
| Family | — | MAX 5000 |
| Device Type | — | EPLD (Erasable/OTP Complex PLD) |
| Macrocells | — | 192 |
| Logic Array Blocks (LABs) | — | 12 |
| User I/O | — | 64 |
| Total Inputs | — | 72 (7 dedicated + 64 I/O) |
| Propagation Delay (tpd) | — | 55 ns (max) |
| Maximum Internal Frequency | — | 100 MHz |
| 供應電壓 | — | 4.5 V to 5.5 V |
| 工作溫度 | — | -40 C to +85 C (industrial) |
| Typical Power Dissipation | — | 600 mW at 5 V / 25 C |
| Technology | — | CMOS, UV-erasable / OTP |
| 封裝 | — | 84-pin PLCC (J-lead), JEDEC S-PQCC-J84 |
| Design Toolchain | — | Altera MAX+plus II |