EPM7096QI100-15 vs EPM7096QC100-10 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM7096QI100-15 sa pamamagitan ng Altera at EPM7096QC100-10 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Altera
EPM7096QI100-15 EPM7096QI100-15 - MAX 7000 CPLD 96 Macro 76 I/O 15ns | Altera

EPM7096QI100-15 - MAX 7000 CPLD 96 Macro 76 I/O 15ns | Altera

EPM7096QI100-15 ⚠ Huling Pagbili

Pagsanggunian na paghahambing

Parametro EPM7096QI100-15 EPM7096QC100-10
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Huling Pagbili Obsolete
Series MAX 7000 —
Device Type CPLD - Complex Programmable Logic Device —
Programmable Type EE PLD (EEPROM-based, in-system programmable) —
Number of Macrocells 96 —
Number of Logic Array Blocks (LABs) 4 —
Number of Usable Gates 1,800 —
Number of I/O Pins 76 —
Maximum Propagation Delay (tPD) 15 ns —
Supply Voltage (VCC) 4.5 V to 5.5 V 4.75 V to 5.25 V
Temperature na Operasyon -40C to +85C (industrial, per Q-suffix) 0 °C to +70 °C (commercial)
Packhaging / Kaso 100-BQFP (BQFP-100) —
Uri ng Pagpapasok Surface Mount Surface Mount
Programming Interface IEEE Std. 1149.1 JTAG (ISP) ByteBlaster / parallel (JTAG ISP on MAX 7000S variants)
Packaging Tray —
Tindminan RoHS [DATA_NEEDED: RoHS compliance status not stated in verified data] [DATA_NEEDED: RoHS compliance status]
Family — MAX 7000
Macrocells — 96
Logic Array Blocks — 4
User I/O Pins — 76
Propagation Delay (tPD) — 10 ns
Maximum Operating Frequency — 100 MHz
Technology — EEPROM-based CMOS
Boundary Scan — IEEE Std. 1149.1 (JTAG) on MAX 7000S
PCI Compliance — Yes (PCI SIG Local Bus Specification Rev. 2.2 at -10 speed grade)
Packhaging — 100-pin PQFP (R-PQFP-G100, 20×14 mm, 0.65 mm pitch)

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