EPM7096QI100-15 vs EPM7096QC100-10 比較
詳細並排比較 EPM7096QI100-15 由 Altera 與 EPM7096QC100-10 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EPM7096QC100-10 - 96-Macrocell MAX 7000 CPLD, 10ns, PQFP-100 | Altera
EPM7096QC100-10 Obsolete規格比較
| 參數 | EPM7096QI100-15 | EPM7096QC100-10 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 最後購買 | Obsolete |
| Series | MAX 7000 | — |
| Device Type | CPLD - Complex Programmable Logic Device | — |
| Programmable Type | EE PLD (EEPROM-based, in-system programmable) | — |
| Number of Macrocells | 96 | — |
| Number of Logic Array Blocks (LABs) | 4 | — |
| Number of Usable Gates | 1,800 | — |
| Number of I/O Pins | 76 | — |
| Maximum Propagation Delay (tPD) | 15 ns | — |
| Supply Voltage (VCC) | 4.5 V to 5.5 V | 4.75 V to 5.25 V |
| 工作溫度 | -40C to +85C (industrial, per Q-suffix) | 0 °C to +70 °C (commercial) |
| 封裝 / 外殼 | 100-BQFP (BQFP-100) | — |
| 安裝類型 | Surface Mount | Surface Mount |
| Programming Interface | IEEE Std. 1149.1 JTAG (ISP) | ByteBlaster / parallel (JTAG ISP on MAX 7000S variants) |
| Packaging | Tray | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance status not stated in verified data] | [DATA_NEEDED: RoHS compliance status] |
| Family | — | MAX 7000 |
| Macrocells | — | 96 |
| Logic Array Blocks | — | 4 |
| User I/O Pins | — | 76 |
| Propagation Delay (tPD) | — | 10 ns |
| Maximum Operating Frequency | — | 100 MHz |
| Technology | — | EEPROM-based CMOS |
| Boundary Scan | — | IEEE Std. 1149.1 (JTAG) on MAX 7000S |
| PCI Compliance | — | Yes (PCI SIG Local Bus Specification Rev. 2.2 at -10 speed grade) |
| 封裝 | — | 100-pin PQFP (R-PQFP-G100, 20×14 mm, 0.65 mm pitch) |