EPM7128AETC144-10 vs EPM7128AETC144-7N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM7128AETC144-10 sa pamamagitan ng Altera at EPM7128AETC144-7N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM7128AETC144-10 EPM7128AETC144-7N
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND Aktibo
Family MAX 7000A MAX 7000A
Macrocells 128 —
Usable Gates 2,500 —
Logic Array Blocks (LABs) 8 —
Maximum User I/Os 36 —
Pin-to-pin Logic Delay (tPD) 10 ns —
Maximum Internal Counter Frequency 98 MHz —
Supply Voltage (Core) 3.3 V —
I/O Voltage Tolerance 2.5 V / 3.3 V / 5 V —
Temperature na Operasyon 0C to +70C (Commercial) 0C to +70C (commercial)
Packhaging 144-pin TQFP (also referred to as LQFP-144) 144-pin TQFP
Programming Interface JTAG (IEEE Std. 1149.1) and ByteBlaster —
Non-volatile Memory EEPROM, instant-on —
Global Clocks / Global OE 2 / 2 —
Uri ng Pagpapasok Surface Mount Surface Mount
Level ng MSL MSL 3 (per JEDEC J-STD-020) —
Tindminan RoHS [DATA_NEEDED: rohs status from manufacturer] Compliant
Device Type — CPLD (Complex Programmable Logic Device)
Logic Gates — 2500 (2.5K gates)
Macro Cells — 128
User I/Os — 36 (in 144-pin TQFP)
Maximum Operating Frequency — 129.9 MHz
Pin-to-Pin Delay — 7.5 ns
Propagation Delay (tpd) — 7.5 ns
Supply Voltage (VCCINT) — 3.3 V
Process Technology — CMOS, EEPROM-based
Programmability — In-System Programmable (ISP) via JTAG
Boundary-Scan Test — IEEE Std 1149.1 (JTAG)
Pin-Compatible With — MAX 7000S 5.0V family (144-pin TQFP)
Lead-Free — Yes

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