EPM7128SLC84-6N vs EPM7128SLI84-10N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM7128SLC84-6N sa pamamagitan ng Intel at EPM7128SLI84-10N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EPM7128SLC84-6N - MAX 7000S CPLD, 128 Macro, 6ns, 84-PLCC | Intel
EPM7128SLC84-6N ⚠ Huling PagbiliAltera
EPM7128SLI84-10N - MAX 7000S CPLD 128 Macro 10ns 84-PLCC | Intel / Altera
EPM7128SLI84-10N NrndPagsanggunian na paghahambing
| Parametro | EPM7128SLC84-6N | EPM7128SLI84-10N |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | NRND |
| Family | MAX 7000S | MAX 7000S |
| Device System Gates | 2500 | — |
| Number of Macro Cells | 128 | — |
| Number of User I/Os | 68 | — |
| Number of Logic Blocks/Elements | 8 | — |
| Number of Global Clocks | 2 | — |
| Product Terms per Macro Cell | 32 | — |
| Maximum Operating Frequency | 147.1 MHz | — |
| Pin-to-Pin Delay (Speed Grade) | 6 ns | — |
| Volte ng Pagbibigay | 5 V | — |
| Process Technology | CMOS, EEPROM | CMOS EEPROM |
| Program Memory Type | EEPROM | — |
| In-System Programmability | Yes (ISP via JTAG) | — |
| Packhaging | 84-pin PLCC (J-lead) | 84-pin PLCC (J-Lead) |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | -40 C to +85 C (Industrial) |
| Tindminan RoHS | Non-Compliant (legacy 5V part) | [DATA_NEEDED: RoHS compliance per latest Intel/Altera declaration] |
| Logic Cells / Macro Cells | — | 128 macro cells |
| Usable Gates | — | 2,500 |
| Number of Logic Elements / Blocks | — | 16 Logic Array Blocks (LABs) |
| User I/Os | — | 68 |
| Propagation Delay (tPD) | — | 10 ns |
| Maximum Frequency (fMAX) | — | 125 MHz |
| Supply Voltage (VCCINT) | — | 4.75 V to 5.25 V (5 V typical) |
| I/O Voltage Tolerance | — | 3.3 V / 5 V MultiVolt I/O |
| Programmability | — | In-system programmable (ISP), non-volatile EEPROM |
| Boundary-Scan (JTAG) | — | IEEE Std 1149.1 compliant |
| Uri ng Pagpapasok | — | Surface Mount |
| Lead-Free | — | [DATA_NEEDED: lead-free per latest Intel/Altera declaration] |