EPM7160STI100-10 vs EPM7160STC100-10 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM7160STI100-10 sa pamamagitan ng Altera at EPM7160STC100-10 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM7160STI100-10 EPM7160STC100-10
Brand Altera Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Huling Pagbili
Family MAX 7000S MAX 7000S
Macrocells 160 —
Usable Gates 3,200 3,200
User I/Os 84 84
Logic Elements / Blocks 16 Logic Array Blocks (LABs) —
Propagation Delay (tPD) 10 ns —
Maximum Operating Frequency 100 MHz —
Internal Supply Voltage 4.75 V to 5.25 V —
I/O Supply Voltage 5.0 V —
Programmable Type In-System Programmable (EEPROM) —
Temperature na Operasyon -40 C to +85 C (Industrial) 0 C to +70 C (commercial)
Packhaging TQFP-100 (100-pin Thin Quad Flat Pack) 100-pin TQFP
Uri ng Pagpapasok Surface Mount Surface Mount
JTAG / Boundary Scan IEEE Std. 1149.1 compliant —
PCI Compliance PCI Local Bus Specification Rev. 2.2 (for -10 speed grade) —
Tindminan RoHS [DATA_NEEDED: RoHS status - not explicitly stated in provided data] Non-RoHS (legacy Altera part; -10N variant is RoHS)
Level ng MSL [DATA_NEEDED: MSL rating] —
Lead-Free [DATA_NEEDED: lead-free status] —
Device Type — CPLD (Complex Programmable Logic Device)
Macro Cells — 160
Logic Elements — 160 macrocells / 10 Logic Array Blocks
Supply Voltage (VCC) — 5.0 V (4.75 V - 5.25 V)
Propagation Delay (tPD1) — 10 ns
Global Clock Setup Time — 6 ns
Internal Counter Frequency — 100 MHz
Technology — CMOS, EEPROM-based
In-System Programmability — Yes (IEEE 1149.1 JTAG)

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