EPM9320ALC84-10 vs EPM9320ALC84-15 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM9320ALC84-10 sa pamamagitan ng Intel at EPM9320ALC84-15 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM9320ALC84-10 EPM9320ALC84-15
Brand Intel Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete NRND
Family MAX 9000 MAX 9000 CPLD
Device EPM9320 —
Macrocells 320 320
Logic Array Blocks (LABs) 16 16
Maximum User I/O Pins 52 —
Dedicated Inputs 16 —
Speed Grade -10 (10 ns pin-to-pin delay) —
Pin-to-Pin Delay (tPD) 10 ns —
Supply Voltage (VCCINT) 5.0 V —
In-System Programmability 5.0 V ISP via IEEE 1149.1 JTAG —
Technology CMOS EEPROM-based, third-generation MAX CMOS, EEPROM-based configuration
PCI Compliance PCI Local Bus Specification Rev. 2.2 (speed grade -10) —
Packhaging 84-pin PLCC (J-Lead) 84-pin PLCC (S-PQCC-J84, J-lead)
Temperature na Operasyon [DATA_NEEDED: commercial/industrial grade] -40C to +85C (industrial)
Uri ng Pagpapasok Surface Mount / Through-Hole (PLCC socket) Through-hole / socket
Tindminan RoHS [DATA_NEEDED] [DATA_NEEDED: rohs status]
Non-Volatile Configuration Yes (EEPROM cell, powers up in known state) —
Architecture MAX (Multiple Array MatriX) with FastTrack Interconnect —
Usable Gates — 6000
Propagation Delay (tPD) — 16 ns
Supply Voltage (VCC) — 4.75 V to 5.25 V (5 V nominal)
User I/O — 56
Programming Interface — JTAG (IEEE 1149.1) / ISP
Level ng Sensitivity sa Asid ng Moisture (MSL) — MSL-3 (168 hours per fpgalink.com)
Lead-Free / Halogen-Free — [DATA_NEEDED: lead free status]
RoHS3 Compliance — ROHS3 Compliant (per fpgalink.com listing)

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