EPM9320ALC84-10 vs EPM9320ALC84-15 比較
詳細並排比較 EPM9320ALC84-10 由 Intel 與 EPM9320ALC84-15 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM9320ALC84-10 | EPM9320ALC84-15 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Family | MAX 9000 | MAX 9000 CPLD |
| Device | EPM9320 | — |
| Macrocells | 320 | 320 |
| Logic Array Blocks (LABs) | 16 | 16 |
| Maximum User I/O Pins | 52 | — |
| Dedicated Inputs | 16 | — |
| Speed Grade | -10 (10 ns pin-to-pin delay) | — |
| Pin-to-Pin Delay (tPD) | 10 ns | — |
| Supply Voltage (VCCINT) | 5.0 V | — |
| In-System Programmability | 5.0 V ISP via IEEE 1149.1 JTAG | — |
| Technology | CMOS EEPROM-based, third-generation MAX | CMOS, EEPROM-based configuration |
| PCI Compliance | PCI Local Bus Specification Rev. 2.2 (speed grade -10) | — |
| 封裝 | 84-pin PLCC (J-Lead) | 84-pin PLCC (S-PQCC-J84, J-lead) |
| 工作溫度 | [DATA_NEEDED: commercial/industrial grade] | -40C to +85C (industrial) |
| 安裝類型 | Surface Mount / Through-Hole (PLCC socket) | Through-hole / socket |
| RoHS 狀態 | [DATA_NEEDED] | [DATA_NEEDED: rohs status] |
| Non-Volatile Configuration | Yes (EEPROM cell, powers up in known state) | — |
| Architecture | MAX (Multiple Array MatriX) with FastTrack Interconnect | — |
| Usable Gates | — | 6000 |
| Propagation Delay (tPD) | — | 16 ns |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (5 V nominal) |
| User I/O | — | 56 |
| Programming Interface | — | JTAG (IEEE 1149.1) / ISP |
| 濕度敏感等級 (MSL) | — | MSL-3 (168 hours per fpgalink.com) |
| Lead-Free / Halogen-Free | — | [DATA_NEEDED: lead free status] |
| RoHS3 Compliance | — | ROHS3 Compliant (per fpgalink.com listing) |