EPM9320ALC84-10 vs EPM9320ALC84-15 Comparison

Detailed side-by-side comparison of EPM9320ALC84-10 by Intel and EPM9320ALC84-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM9320ALC84-10 EPM9320ALC84-15
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $19.80 $9.95
Family MAX 9000 MAX 9000 CPLD
Device EPM9320 β€”
Macrocells 320 320
Logic Array Blocks (LABs) 16 16
Maximum User I/O Pins 52 β€”
Dedicated Inputs 16 β€”
Speed Grade -10 (10 ns pin-to-pin delay) β€”
Pin-to-Pin Delay (tPD) 10 ns β€”
Supply Voltage (VCCINT) 5.0 V β€”
In-System Programmability 5.0 V ISP via IEEE 1149.1 JTAG β€”
Technology CMOS EEPROM-based, third-generation MAX CMOS, EEPROM-based configuration
PCI Compliance PCI Local Bus Specification Rev. 2.2 (speed grade -10) β€”
Package 84-pin PLCC (J-Lead) 84-pin PLCC (S-PQCC-J84, J-lead)
Operating Temperature [DATA_NEEDED: commercial/industrial grade] -40C to +85C (industrial)
Mounting Type Surface Mount / Through-Hole (PLCC socket) Through-hole / socket
RoHS Status [DATA_NEEDED] [DATA_NEEDED: rohs status]
Non-Volatile Configuration Yes (EEPROM cell, powers up in known state) β€”
Architecture MAX (Multiple Array MatriX) with FastTrack Interconnect β€”
Usable Gates β€” 6000
Propagation Delay (tPD) β€” 16 ns
Supply Voltage (VCC) β€” 4.75 V to 5.25 V (5 V nominal)
User I/O β€” 56
Programming Interface β€” JTAG (IEEE 1149.1) / ISP
Moisture Sensitivity Level (MSL) β€” MSL-3 (168 hours per fpgalink.com)
Lead-Free / Halogen-Free β€” [DATA_NEEDED: lead free status]
RoHS3 Compliance β€” ROHS3 Compliant (per fpgalink.com listing)

Datasheets & Resources

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