EPM9320ALI84-10N vs EPM9320LC84-20N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM9320ALI84-10N sa pamamagitan ng Altera at EPM9320LC84-20N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM9320ALI84-10N EPM9320LC84-20N
Brand Altera Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Aktibo
Family MAX 9000 —
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Architecture MAX (Multiple Array MatriX), 3rd generation —
Process Technology CMOS EEPROM —
Usable Gates 6,000 to 12,000 6,000
Macrocells 320 320
Logic Array Blocks (LABs) 20 —
User I/O Pins 56 —
Pin-to-Pin Delay 10 ns —
Maximum Counter Frequency 144.9 MHz —
VCCINT (Core Supply) 5.0 V —
VCCIO (I/O Supply) 3.3 V or 5.0 V —
Input Logic Levels TTL-compatible (at 5.0 V VCCINT) —
In-System Programmability Yes (IEEE Std. 1149.1 JTAG) —
Packhaging 84-pin PLCC (J-lead, 1.270 mm pitch) —
Uri ng Pagpapasok Surface Mount (PLCC socket compatible) Surface Mount (J-bend)
Temperature na Operasyon -40C to +85C (industrial) 0 C to +70 C (Commercial)
Configuration Memory EEPROM, non-volatile —
Series — MAX 9000
Logic Family — CMOS (EEPROM-based)
User I/Os — 60
Bilang ng Pins — 84
Package Type — Plastic Leaded Chip Carrier (PLCC-84, J-bend)
Package Code — QCCJ
Propagation Delay (tPD) — 16 ns
Internal Frequency — 118 MHz
Supply Voltage (VCC) — 5 V
Programming — 5.0-V In-System Programmable via JTAG (IEEE 1149.1)
Terminal Form — J BEND
Level ng MSL — [DATA_NEEDED: MSL moisture sensitivity level]
Tindminan RoHS — [DATA_NEEDED: RoHS compliance status]

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