EPM9320ALI84-10N vs EPM9320LC84-20N 比較
詳細並排比較 EPM9320ALI84-10N 由 Altera 與 EPM9320LC84-20N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM9320ALI84-10N | EPM9320LC84-20N |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | 啟用中 |
| Family | MAX 9000 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Architecture | MAX (Multiple Array MatriX), 3rd generation | — |
| Process Technology | CMOS EEPROM | — |
| Usable Gates | 6,000 to 12,000 | 6,000 |
| Macrocells | 320 | 320 |
| Logic Array Blocks (LABs) | 20 | — |
| User I/O Pins | 56 | — |
| Pin-to-Pin Delay | 10 ns | — |
| Maximum Counter Frequency | 144.9 MHz | — |
| VCCINT (Core Supply) | 5.0 V | — |
| VCCIO (I/O Supply) | 3.3 V or 5.0 V | — |
| Input Logic Levels | TTL-compatible (at 5.0 V VCCINT) | — |
| In-System Programmability | Yes (IEEE Std. 1149.1 JTAG) | — |
| 封裝 | 84-pin PLCC (J-lead, 1.270 mm pitch) | — |
| 安裝類型 | Surface Mount (PLCC socket compatible) | Surface Mount (J-bend) |
| 工作溫度 | -40C to +85C (industrial) | 0 C to +70 C (Commercial) |
| Configuration Memory | EEPROM, non-volatile | — |
| Series | — | MAX 9000 |
| Logic Family | — | CMOS (EEPROM-based) |
| User I/Os | — | 60 |
| 腳位數 | — | 84 |
| Package Type | — | Plastic Leaded Chip Carrier (PLCC-84, J-bend) |
| Package Code | — | QCCJ |
| Propagation Delay (tPD) | — | 16 ns |
| Internal Frequency | — | 118 MHz |
| Supply Voltage (VCC) | — | 5 V |
| Programming | — | 5.0-V In-System Programmable via JTAG (IEEE 1149.1) |
| Terminal Form | — | J BEND |
| MSL 等級 | — | [DATA_NEEDED: MSL moisture sensitivity level] |
| RoHS 狀態 | — | [DATA_NEEDED: RoHS compliance status] |