EPM9320GC280-20 vs EPM9320GC280-15 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9320GC280-20 sa pamamagitan ng Altera at EPM9320GC280-15 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM9320GC280-15 - 320-Macrocell MAX 9000 CPLD, 15ns, CPGA-280 | Altera
EPM9320GC280-15 ObsoletePagsanggunian na paghahambing
| Parametro | EPM9320GC280-20 | EPM9320GC280-15 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 9000 | MAX 9000 (EPM9320) |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD - Complex Programmable Logic Device |
| Macrocells | 320 | 320 |
| Usable Gates | 6000 (approx.) | 6,000 |
| Logic Array Blocks (LABs) | 20 (16 macrocells each, typical for MAX 9000) | 20 (16 macrocells per LAB) |
| Maximum Operating Frequency | 100 MHz (internal counter) | — |
| Propagation Delay (tpd) | 23 ns (approx., -20 speed grade) | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 4.75 V to 5.25 V |
| Technology | CMOS EEPROM | — |
| In-System Programmability | Yes (5.0-V ISP via JTAG) | — |
| JTAG Support | IEEE Std. 1149.1 compliant | — |
| Packhaging | 280-pin Ceramic Pin Grid Array (CPGA) | 280-pin Ceramic Pin Grid Array (CPGA-280) |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature grade] | 0 C to +70 C (commercial) |
| Uri ng Pagpapasok | Through-Hole (PGA socket) | Through-hole (PGA socket) |
| Tindminan RoHS | unknown | ROHS3 compliant (per fpgalink listing) |
| Configuration Memory | EEPROM (non-volatile, instant-on) | — |
| Architecture | — | CMOS EEPROM-based, Multiple Array MatriX (MAX) |
| Pin-to-Pin Propagation Delay | — | 15 ns |
| Maximum Internal Frequency | — | 117.6 MHz |
| Maximum User I/O Pins | — | 164 |
| I/O Voltage Levels | — | 3.3 V or 5 V (configurable) |
| Programmability | — | 5.0-V in-system programmable (ISP) via IEEE 1149.1 JTAG |
| Level ng MSL | — | 3 (168 hours) |
| Technology Node | — | CMOS EEPROM, third-generation MAX |