EPM9320LC84-20N vs EPM9320LC84-10 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9320LC84-20N sa pamamagitan ng Intel at EPM9320LC84-10 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EPM9320LC84-20N - 320-Cell MAX 9000 CPLD, 84-PLCC | Intel / Altera
EPM9320LC84-20N ✓ NakahandaPagsanggunian na paghahambing
| Parametro | EPM9320LC84-20N | EPM9320LC84-10 |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | NRND |
| Series | MAX 9000 | — |
| Logic Family | CMOS (EEPROM-based) | — |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Usable Gates | 6,000 | 6000 (typical) |
| Macrocells | 320 | 320 |
| User I/Os | 60 | — |
| Bilang ng Pins | 84 | — |
| Package Type | Plastic Leaded Chip Carrier (PLCC-84, J-bend) | — |
| Package Code | QCCJ | — |
| Propagation Delay (tPD) | 16 ns | — |
| Internal Frequency | 118 MHz | — |
| Supply Voltage (VCC) | 5 V | 5.0 V (typical, see datasheet) |
| Temperature na Operasyon | 0 C to +70 C (Commercial) | 0C to +70C (commercial) [DATA_NEEDED: exact grade suffix] |
| Programming | 5.0-V In-System Programmable via JTAG (IEEE 1149.1) | — |
| Uri ng Pagpapasok | Surface Mount (J-bend) | Surface Mount (PLCC socket also common) |
| Terminal Form | J BEND | — |
| Level ng MSL | [DATA_NEEDED: MSL moisture sensitivity level] | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | ROHS3 Compliant (per fpgalink listing) |
| Family | — | MAX 9000 EPLD |
| Device | — | EPM9320 |
| Logic Array Blocks (LABs) | — | 16 |
| Maximum User I/O Pins | — | 168 (varies by package) |
| Pin-to-Pin Logic Delay (tPD) | — | 10 ns |
| Maximum Frequency (fCNT) | — | [DATA_NEEDED: fCNT in MHz] |
| Process Technology | — | 0.7 µm CMOS EEPROM/UV-EPROM |
| Packhaging | — | 84-pin PLCC (JEDEC MO-047) |
| Programming Interface | — | JTAG (IEEE 1149.1) boundary-scan, Altera ByteBlaster compatible |
| Configuration | — | Non-volatile EEPROM (instant-on, no boot PROM) |
| Level ng Sensitivity sa Asid ng Moisture (MSL) | — | MSL-3, 168 hours (per fpgalink listing) |
| Manufacturer Lead Time | — | 1-7 days (per fpgalink listing) |