EPM9320RI208-20N vs EPM9320RC208-20N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM9320RI208-20N sa pamamagitan ng Altera at EPM9320RC208-20N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM9320RI208-20N EPM9320RC208-20N
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND Obsolete
Device Family MAX 9000 (EPM9320) MAX 9000
Logic Type EEPROM-based Complex Programmable Logic Device (CPLD) Complex Programmable Logic Device (CPLD)
Macrocells 320 —
Flip-Flops 484 —
Propagation Delay (tPD) 20 ns —
Supply Voltage (VCC) 5.0 V —
I/O Voltage Tolerance 3.3 V or 5 V configurable —
Packhaging 208-pin PQFP (Plastic Quad Flat Pack) 208-pin RQFP (PowerQuad II)
Package Lead Pitch 0.500 mm —
Number of Terminals 208 —
Hanay ng Temperature na Operasyon -40C to +85C (Industrial) —
In-System Programmability Yes, 5.0 V ISP via JTAG Yes, via IEEE Std. 1149.1 JTAG
JTAG Interface IEEE Std. 1149.1 compliant —
Configuration Memory EEPROM (non-volatile) EEPROM (non-volatile)
Dedicated Input Pins 4 (low-skew global distribution) —
Minimum DC Input on I/O Pins -0.5 V —
Minimum DC Input on Dedicated Inputs -0.3 V —
Input Undershoot/ Overshoot -2.0 V / 7.0 V for <20 ns (no-load) —
Uri ng Pagpapasok Surface Mount Surface Mount
Tindminan RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Usable Gates — 6,000
Macro Cells — 320
Logic Array Blocks — 20
Maximum Pin-to-Pin Delay (tPD) — 20 ns
Maximum Operating Frequency — 100 MHz
Volte ng Pagbibigay — 5.0 V
User I/O Pins — 168
Temperature na Operasyon — [DATA_NEEDED: operating temperature range]
Lead Finish — [DATA_NEEDED: lead finish]
Level ng MSL — [DATA_NEEDED: MSL level]

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