EPM9320RI208-20N vs EPM9320RC208-20N 比較
詳細並排比較 EPM9320RI208-20N 由 Altera 與 EPM9320RC208-20N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM9320RI208-20N | EPM9320RC208-20N |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Device Family | MAX 9000 (EPM9320) | MAX 9000 |
| Logic Type | EEPROM-based Complex Programmable Logic Device (CPLD) | Complex Programmable Logic Device (CPLD) |
| Macrocells | 320 | — |
| Flip-Flops | 484 | — |
| Propagation Delay (tPD) | 20 ns | — |
| Supply Voltage (VCC) | 5.0 V | — |
| I/O Voltage Tolerance | 3.3 V or 5 V configurable | — |
| 封裝 | 208-pin PQFP (Plastic Quad Flat Pack) | 208-pin RQFP (PowerQuad II) |
| Package Lead Pitch | 0.500 mm | — |
| Number of Terminals | 208 | — |
| 工作溫度範圍 | -40C to +85C (Industrial) | — |
| In-System Programmability | Yes, 5.0 V ISP via JTAG | Yes, via IEEE Std. 1149.1 JTAG |
| JTAG Interface | IEEE Std. 1149.1 compliant | — |
| Configuration Memory | EEPROM (non-volatile) | EEPROM (non-volatile) |
| Dedicated Input Pins | 4 (low-skew global distribution) | — |
| Minimum DC Input on I/O Pins | -0.5 V | — |
| Minimum DC Input on Dedicated Inputs | -0.3 V | — |
| Input Undershoot/ Overshoot | -2.0 V / 7.0 V for <20 ns (no-load) | — |
| 安裝類型 | Surface Mount | Surface Mount |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Usable Gates | — | 6,000 |
| Macro Cells | — | 320 |
| Logic Array Blocks | — | 20 |
| Maximum Pin-to-Pin Delay (tPD) | — | 20 ns |
| Maximum Operating Frequency | — | 100 MHz |
| 供應電壓 | — | 5.0 V |
| User I/O Pins | — | 168 |
| 工作溫度 | — | [DATA_NEEDED: operating temperature range] |
| Lead Finish | — | [DATA_NEEDED: lead finish] |
| MSL 等級 | — | [DATA_NEEDED: MSL level] |