EPM9560ARC240-10 vs EPM9560ARC208-10 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560ARC240-10 sa pamamagitan ng Altera at EPM9560ARC208-10 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM9560ARC240-10 EPM9560ARC208-10
Brand Altera Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family MAX 9000 —
Device Type CPLD (Complex Programmable Logic Device) —
Architecture Multiple Array MatriX (MAX) - third generation —
Usable Gates 12,000 12,000 gates
Macrocells 560 560 macrocells
User I/Os (this package) 191 (per Mouser listing) —
Internal Frequency 144.9 MHz 144.9 MHz
Propagation Delay (tpd) 11.4 ns —
Supply Voltage - Internal (VCCINT) 5.0 V —
I/O Supply Voltage (VCCIO) 3.3 V or 5.0 V (selectable) —
Process Technology CMOS EEPROM —
Packhaging 240-pin PowerQuad QFP (RQFP / EAR240) 208-pin RQFP (PowerQuad Flat Pack) with exposed pad
Temperature na Operasyon 0C to +70C (commercial) 0 C to +70 C (commercial)
Configuration Memory EEPROM (non-volatile, in-system programmable) —
Logic Family CMOS CMOS
Tindminan RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Device Family — MAX 9000A (Multiple Array MatriX)
Programmable Logic Type — CPLD (Complex Programmable Logic Device)
Logic Array Blocks — 35 LABs
User I/O Pins — 153 I/O
Propagation Delay (tPD) — 10 ns (speed grade -10)
Volte ng Pagbibigay — 5.0 V
Configuration Technology — EEPROM (non-volatile, in-system programmable)
JTAG Interface — IEEE 1149.1 boundary-scan (ISP)
Uri ng Pagpapasok — Surface Mount
Bilang ng Pin — 208 pins

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