EPM9560GC280-15 vs EPM9560GC280-20N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560GC280-15 sa pamamagitan ng Altera at EPM9560GC280-20N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM9560GC280-15 EPM9560GC280-20N
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete NRND
Family MAX 9000 MAX 9000
Device Type EE PLD (CMOS EEPROM-based CPLD) CPLD (Complex Programmable Logic Device)
Macro Cells 560 —
Typical Gates 12,000 —
Maximum Operating Frequency 117.6 MHz —
Propagation Delay (tpd) 15 ns (speed grade -15) —
Propagation Delay (alternate datasheet figure) 16.6 ns —
Supply Voltage (VCCINT/VCCIO) 5.0 V —
Operating Temperature (Commercial) 0C to +70C —
Package Type CPGA-280 (Ceramic Pin Grid Array, 280 pins) —
Uri ng Pagpapasok Through-Hole —
Programmability In-System Programmable (ISP) via JTAG IEEE 1149.1 —
Technology CMOS EEPROM, 0.5 um process (MAX third-gen) CMOS EEPROM-based
Architecture Multiple Array MatriX (MAX) Multiple Array MatriX (MAX), 3rd generation
Tindminan RoHS Non-compliant (ceramic CPGA, contains lead) [DATA_NEEDED]
Katayuan ng Lifecycle Obsolete (legacy Altera MAX 9000 family) —
Usable Gates — 6,000 to 12,000
Macrocells — 560
User I/O Pins — 212
Pin-to-Pin Delay (tPD) — 20 ns
Maximum Counter Frequency — 144 MHz
Supply Voltage (VCC) — 4.75 V to 5.25 V
I/O Voltage — 3.3 V or 5 V (configurable)
In-System Programmability — Yes (5.0-V ISP via IEEE 1149.1 JTAG)
Packhaging — 280-pin CPGA (Ceramic Pin Grid Array)
Configuration Memory — EEPROM (non-volatile, instant-on)
PCI Compliance — Yes
Temperature na Operasyon — [DATA_NEEDED: industrial/commercial grade]

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