EPM9560RC208-15 vs EPM9560ARC208-10N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560RC208-15 sa pamamagitan ng Altera at EPM9560ARC208-10N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM9560RC208-15 | EPM9560ARC208-10N |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Device Type | EEPROM-based Complex Programmable Logic Device (CPLD) | — |
| Usable Gates | 12,000 gates | 12,000 |
| Macro Cells | 560 macro cells | — |
| Pin-to-Pin Delay | 15 ns | 10 ns |
| Counter Speed | 117.6 MHz | — |
| Volte ng Pagbibigay | 5.0 V | 5 V |
| Configuration Technology | EEPROM (non-volatile) | — |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | Yes (JTAG ISP) |
| Packhaging | 208-pin RQFP (Power Quad Flat Pack) | 208-pin RQFP (PowerQuad II) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | 0 C to +70 C (commercial) |
| Number of I/O Pins | [DATA_NEEDED: number of I/O pins] | — |
| Logic Array Blocks | [DATA_NEEDED: number of logic array blocks] | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | Compliant (N suffix) |
| Speed Grade | -15 (15 ns pin-to-pin) | -10 |
| Architecture | Third-generation Multiple Array MatriX (MAX) | — |
| Macrocells | — | 560 |
| User I/O Pins | — | 153 |
| Internal Counter Frequency | — | 144.9 MHz |
| Technology | — | CMOS EEPROM |
| Configuration Memory | — | EEPROM (non-volatile) |
| Logic Array Blocks (LABs) | — | 20 |
| Lead Finish | — | [DATA_NEEDED: lead finish] |
| Level ng MSL | — | [DATA_NEEDED: MSL level] |