EPM9560RC208-19 vs EPM9560RC208-15 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560RC208-19 sa pamamagitan ng Altera at EPM9560RC208-15 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM9560RC208-19 EPM9560RC208-15
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Device Family MAX 9000 —
Product Type CPLD (Complex Programmable Logic Device) —
Macrocells 560 —
Usable Gates 12,000 12,000 gates
Logic Array Blocks (LABs) [DATA_NEEDED: LAB count] —
Flip-Flops 772 —
User I/O Pins 149 —
Propagation Delay (tPD) 19 ns —
Maximum Frequency [DATA_NEEDED: fMAX] —
Supply Voltage (VCCINT) 5.0 V —
I/O Voltage Tolerance 3.3 V / 5 V —
In-System Programmability Yes (IEEE 1149.1 JTAG) Yes, via IEEE Std. 1149.1 JTAG
Technology CMOS EEPROM —
Packhaging RQFP-208 (208-pin PQFP) 208-pin RQFP (Power Quad Flat Pack)
JEDEC Package Code S-PQFP-G208 —
Temperature na Operasyon [DATA_NEEDED: operating temperature grade] [DATA_NEEDED: operating temperature range]
Uri ng Pagpapasok Surface Mount Surface Mount
Tindminan RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Family — MAX 9000
Device Type — EEPROM-based Complex Programmable Logic Device (CPLD)
Macro Cells — 560 macro cells
Pin-to-Pin Delay — 15 ns
Counter Speed — 117.6 MHz
Volte ng Pagbibigay — 5.0 V
Configuration Technology — EEPROM (non-volatile)
Number of I/O Pins — [DATA_NEEDED: number of I/O pins]
Logic Array Blocks — [DATA_NEEDED: number of logic array blocks]
Speed Grade — -15 (15 ns pin-to-pin)
Architecture — Third-generation Multiple Array MatriX (MAX)

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