EPM9560RC240-15N vs EPM9560RC240-2 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560RC240-15N sa pamamagitan ng Altera at EPM9560RC240-2 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM9560RC240-15N EPM9560RC240-2
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND Obsolete
Series MAX 9000 —
Family MAX 9000 (third-generation Multiple Array MatriX) MAX 9000
Usable Gates 12,000 12,000
Macrocells 560 —
Logic Array Blocks (LABs) 35 —
Maximum User I/O Pins 216 —
Pin-to-Pin Propagation Delay (tPD) 15 ns —
Internal Counter Frequency (fCNT) 145 MHz —
Global Setup Time (tFSU) [DATA_NEEDED: tFSU for -15 grade] —
Clock-to-Output Time (tFCO) [DATA_NEEDED: tFCO for -15 grade] —
Volte ng Pagbibigay 5.0 V 5 V
Logic Family CMOS (EEPROM-based) —
Programmability In-system programmable (IEEE 1532/JTAG) —
Boundary-Scan Test JTAG (IEEE 1149.1) —
Temperature na Operasyon 0C to +70C (Commercial) [DATA_NEEDED: commercial/industrial grade]
Packhaging RQFP-240 (240-pin Plastic Quad Flat Pack) 240-pin RQFP (Metric QFP)
Uri ng Pagpapasok Surface Mount Surface Mount
Tindminan RoHS [DATA_NEEDED: RoHS compliance - older Altera RQFP part] Non-compliant (5V RQFP, pre-RoHS era)
Logic Elements — 560 macrocells
Pin-to-Pin Delay — 2 ns (speed grade -2)
Maximum Frequency — 100 MHz
User I/O Count — 212
Programming Interface — JTAG (IEEE 1149.1), in-system programmable
Non-Volatile Configuration — Yes (EEPROM-based)
Lead-Free — No (legacy Sn/Pb process)
Logic Block Count — [DATA_NEEDED: LAB count]

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