EPM9560RI208-15 vs EPM9560RI208-10N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560RI208-15 sa pamamagitan ng Intel at EPM9560RI208-10N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM9560RI208-15 | EPM9560RI208-10N |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Architecture | CMOS EEPROM-based Multiple Array MatriX (MAX) | CMOS EEPROM-based Multiple Array MatriX (MAX) |
| Macrocells | 560 | — |
| Typical Usable Gates | 12,000 | — |
| User I/Os | 153 | 212 |
| Internal Frequency (max) | 145 MHz | — |
| Propagation Delay (tPD) | 11.4 ns (commercial); 15 ns speed grade | — |
| Logic Family | CMOS | — |
| Bilang ng Pins | 208 | — |
| Package Code | HFQFP (Power Quad Flat Pack, gull-wing) | — |
| Package Type | RQFP-208 | — |
| Supply Voltage (VCC) | 5 V nominal (4.5 V to 5.5 V) | — |
| I/O Voltage Support | 3.3 V or 5 V multi-volt I/O | — |
| Temperature na Operasyon | 0 °C to 70 °C (industrial grade; per package suffix R) | -40C to +85C (Industrial grade, "RI" suffix) |
| In-System Programmability | Yes (JTAG / IEEE 1149.1) | — |
| Boundary-Scan (JTAG) | Compliant | — |
| Configuration Memory | On-chip EEPROM (non-volatile) | On-chip EEPROM (non-volatile) |
| Tindminan RoHS | ROHS3 Compliant | ROHS3 Compliant (per fpgalink) |
| Level ng Sensitivity sa Asid ng Moisture (MSL) | 3 (168 hours) | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Usable Gates | — | 12,000 |
| Macro Cells | — | 560 |
| Register Bits | — | 12,160 |
| Pin-to-Pin Delay | — | 10 ns (speed grade -10) |
| Maximum Frequency | — | 100 MHz to 125 MHz |
| Volte ng Pagbibigay | — | 5 V |
| Packhaging | — | 208-pin RQFP (PQFP) |
| Programming Method | — | In-system via IEEE 1149.1 (JTAG) |
| Level ng MSL | — | 3 (168 Hours) |