EPM9560RI208-15 vs EPM9560RI208-10N Comparison
Detailed side-by-side comparison of EPM9560RI208-15 by Intel and EPM9560RI208-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9560RI208-15 | EPM9560RI208-10N |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Architecture | CMOS EEPROM-based Multiple Array MatriX (MAX) | CMOS EEPROM-based Multiple Array MatriX (MAX) |
| Macrocells | 560 | — |
| Typical Usable Gates | 12,000 | — |
| User I/Os | 153 | 212 |
| Internal Frequency (max) | 145 MHz | — |
| Propagation Delay (tPD) | 11.4 ns (commercial); 15 ns speed grade | — |
| Logic Family | CMOS | — |
| Number of Pins | 208 | — |
| Package Code | HFQFP (Power Quad Flat Pack, gull-wing) | — |
| Package Type | RQFP-208 | — |
| Supply Voltage (VCC) | 5 V nominal (4.5 V to 5.5 V) | — |
| I/O Voltage Support | 3.3 V or 5 V multi-volt I/O | — |
| Operating Temperature | 0 °C to 70 °C (industrial grade; per package suffix R) | -40C to +85C (Industrial grade, "RI" suffix) |
| In-System Programmability | Yes (JTAG / IEEE 1149.1) | — |
| Boundary-Scan (JTAG) | Compliant | — |
| Configuration Memory | On-chip EEPROM (non-volatile) | On-chip EEPROM (non-volatile) |
| RoHS Status | ROHS3 Compliant | ROHS3 Compliant (per fpgalink) |
| Moisture Sensitivity Level (MSL) | 3 (168 hours) | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Usable Gates | — | 12,000 |
| Macro Cells | — | 560 |
| Register Bits | — | 12,160 |
| Pin-to-Pin Delay | — | 10 ns (speed grade -10) |
| Maximum Frequency | — | 100 MHz to 125 MHz |
| Supply Voltage | — | 5 V |
| Package | — | 208-pin RQFP (PQFP) |
| Programming Method | — | In-system via IEEE 1149.1 (JTAG) |
| MSL Level | — | 3 (168 Hours) |