K3KL8L80QM-MUCT vs K3LKBKB0BM-MGCP Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng K3KL8L80QM-MUCT sa pamamagitan ng Samsung Electronics at K3LKBKB0BM-MGCP sa pamamagitan ng Samsung Electronics. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Samsung Electronics
K3LKBKB0BM-MGCP - 32Gbit LPDDR5 DRAM 6400Mbps | Samsung
K3LKBKB0BM-MGCP ✓ NakahandaPagsanggunian na paghahambing
| Parametro | K3KL8L80QM-MUCT | K3LKBKB0BM-MGCP |
|---|---|---|
| Brand | Samsung Electronics | Samsung Electronics |
| Kategorya | Memory ICs | Memory ICs |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Presyo ng Yunit (USD) | — | $46.62 |
| Uri ng Memory | LPDDR5X SDRAM | DRAM (LPDDR5 SDRAM) |
| Density | 32 Gb (4 GB) | — |
| Organisasyon | [DATA_NEEDED: organization (xN bit width)] | 1G x 32 |
| Rate ng Data | [DATA_NEEDED: data rate per pin (Gbps)] | 6400 Mbps per pin |
| Supply Voltage Class | [DATA_NEEDED: VDD/VDDQ voltage] | — |
| Speed Grade | QM (per Samsung part numbering) | — |
| Packhaging | FBGA (original package, 315-ball class) | FBGA-315 |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | -25C to +85C |
| Interface | LPDDR5X channel interface | LPDDR5 x32 |
| Series | LPDDR5X | — |
| Brand | Samsung Semiconductor | — |
| Packaging Suffix | MUCT | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | Compliant |
| Level ng MSL | [DATA_NEEDED: moisture sensitivity level] | [DATA_NEEDED: MSL level] |
| Application Segment | Mobile / AI edge computing | Mobile, embedded, industrial computing |
| Laki ng Memory | — | 32 Gbit |
| Supply Voltage Rails | — | 500 mV, 900 mV, 1.05 V, 1.8 V |
| Technology Generation | — | LPDDR5 (JEDEC LPDDR5 family) |
| Density per Package | — | 4 GB (32 Gbit) |
| Refresh | — | Self-refresh and auto-refresh (LPDDR5 standard) |
| Standby / Deep Sleep | — | LPDDR5 deep-sleep power states |
| Access Time / Latency | — | [DATA_NEEDED: CAS latency] |