MPC8536AVTAQG vs MPC8536EAVTAQG Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng MPC8536AVTAQG sa pamamagitan ng NXP Semiconductors at MPC8536EAVTAQG sa pamamagitan ng NXP Semiconductors. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
NXP Semiconductors
MPC8536EAVTAQG - PowerQUICC III 1GHz e500 MPU | NXP/Freescale
MPC8536EAVTAQG NrndPagsanggunian na paghahambing
| Parametro | MPC8536AVTAQG | MPC8536EAVTAQG |
|---|---|---|
| Brand | NXP Semiconductors | NXP Semiconductors |
| Kategorya | Microcontrollers | Microcontrollers |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Processor Type | PowerPC e500 Microprocessor IC MPC85xx | — |
| Core Architecture | PowerPC e500 (Book-E compliant) | — |
| Number of Cores | 1 | 1 |
| Width ng Data Bus | 32-bit | 32 bit |
| Maksimum na Taktiko ng Oras | 1.0 GHz | 1.0 GHz |
| Core Supply Voltage | 1.0 V | — |
| I/O Voltage | 1.8 V, 2.5 V, 3.3 V | — |
| Packhaging / Kaso | 783-FCPBGA (29x29 mm) | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount (BGA) |
| Memory Controller | DDR2, DDR3 (64-bit with ECC) | — |
| Ethernet | 2x 10/100/1000 Mbps (eTSEC, SGMII) | — |
| USB | USB 2.0 (ULPI interface) | — |
| Security Engine | AES, 3DES, SHA-1/SHA-2, MD-5, public-key acceleration | — |
| Datapath Acceleration | Hardware packet parsing, classification, policing | — |
| Local Bus | 16-bit data, 32-bit address | — |
| Operating Temperature Grade | Commercial | — |
| Processor Series | — | MPC85xx (PowerQUICC III) |
| Core | — | PowerPC e500, 32-bit |
| Packhaging | — | 783-FCPBGA (29x29 mm) |
| Encryption Support | — | Yes ('E' suffix indicates encryption-enabled silicon) |
| Temperature na Operasyon | — | [DATA_NEEDED: operating temperature range] |
| Volte ng Pagbibigay | — | [DATA_NEEDED: core/IO supply voltage] |
| Integrated Peripherals | — | QUICC Engine, DDR controller, Gigabit Ethernet, PCI Express |
| Instruction Set Architecture | — | Power Architecture (Book-E) |
| On-chip Cache | — | [DATA_NEEDED: L1/L2 cache configuration] |
| Level ng MSL | — | [DATA_NEEDED: MSL rating] |
| Tindminan RoHS | — | [DATA_NEEDED: RoHS compliance] |