RTAX250SL-CG624E vs RTAX250S-CG624E Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng RTAX250SL-CG624E sa pamamagitan ng Microchip Technology at RTAX250S-CG624E sa pamamagitan ng Microchip Technology. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Microchip Technology
RTAX250SL-CG624E - 250K-Gate Rad-Tolerant FPGA | Microchip
RTAX250SL-CG624E ✓ NakahandaMicrochip Technology
RTAX250S-CG624E - 250K-Gate Rad-Tolerant FPGA | Microchip
RTAX250S-CG624E ✓ NakahandaPagsanggunian na paghahambing
| Parametro | RTAX250SL-CG624E | RTAX250S-CG624E |
|---|---|---|
| Brand | Microchip Technology | Microchip Technology |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | RTAX-S/SL Radiation-Tolerant FPGA | RTAX-S radiation-tolerant FPGA |
| System Gates | 250000 | 250000 gates |
| Logic Cells (CLBs) | 2816 | 2816 |
| Maximum Frequency | 649 MHz | — |
| Process Technology | 0.15 um CMOS | 0.15 um CMOS |
| Core Supply Voltage | 1.5 V | 1.5 V |
| Supply Voltage Tolerance | +/-0.15 V | — |
| Maximum Combinatorial Delay | 0.93 ns | — |
| Packhaging | 624-Pin CCGA (Ceramic Column Grid Array) | — |
| Temperature na Operasyon | -55C to +125C | -55C to +125C |
| Logic Family | CMOS | CMOS |
| Radiation Tolerance | SEU-hardened registers; SEU rate < 10-10 errors/bit-day | — |
| Embedded Memory | Embedded SRAM with built-in FIFO control logic | — |
| Clocking | Segmentable clocks, chip-wide highway routing | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | — |
| Programmability | Live at power-up, true single-chip | — |
| Maximum Toggle Frequency | — | 649 MHz |
| CLB Combinatorial Delay (max) | — | 0.930 ns |
| Package Type | — | CCGA-624 (ceramic column grid array, 624 pins) |
| Programming Technology | — | Antifuse (one-time programmable) |
| SEU Hardening | — | SEU-hardened registers, no external TMR required |
| SEU Immunity | — | Immune to single-event upsets to specified LET threshold; SEU rate < 10-10 errors/bit-day |
| Power-Up Behavior | — | Live at power-up (true single-chip) |
| Target Application | — | Space-flight systems |