THS1230CDWRG4 vs THS1230CDWR Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng THS1230CDWRG4 sa pamamagitan ng Texas Instruments at THS1230CDWR sa pamamagitan ng Texas Instruments. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Texas Instruments
THS1230CDWRG4 - 12-Bit 30 MSPS Low-Power ADC | Texas Instruments
THS1230CDWRG4 ✓ NakahandaTexas Instruments
THS1230CDWR - 12-Bit 30 MSPS Low-Power ADC | Texas Instruments
THS1230CDWR ✓ NakahandaPagsanggunian na paghahambing
| Parametro | THS1230CDWRG4 | THS1230CDWR |
|---|---|---|
| Brand | Texas Instruments | Texas Instruments |
| Kategorya | ADC/DAC | ADC/DAC |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Pangangasiwaan | 12 bits | 12 bits |
| Sample Rate | 30 MSPS | 30 MSPS |
| Number of Inputs | 1 (single channel, configurable) | — |
| Input Configuration | Single-ended, single-ended w/ offset, differential | — |
| Analog Input Range | -2 V to +2 V | — |
| Volte ng Pagbibigay | 3.3 V (single supply) | — |
| Kuru-kuryente ng Pagbibigay | [DATA_NEEDED: typical supply current in mA] | — |
| Power-Down Mode | Yes | Yes (hardware PD pin) |
| Output Interface | Parallel CMOS | — |
| ADC Architecture | Pipelined | — |
| Temperature na Operasyon | -40 C to +85 C | 0 °C to +70 °C (C-grade commercial) |
| Packhaging | 28-SOIC (DW), 0.295 inch (7.50 mm) width | 28-pin SOIC (DW), 7.50 mm body width, tape and reel |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Level ng MSL | [DATA_NEEDED: MSL moisture sensitivity level] | [DATA_NEEDED: MSL level] |
| Tindminan RoHS | Compliant | Compliant |
| Number of Channels | — | 1 |
| Supply Voltage (AVDD) | — | 3.3 V (single supply) |
| Architecture | — | Pipelined / multi-stage with digital error correction |
| Input Type | — | Configurable: single-ended, single-ended with offset, or differential |
| Analog Input Bandwidth | — | [DATA_NEEDED: analog input bandwidth MHz] |
| SNR | — | [DATA_NEEDED: SNR dBFS at fIN] |
| SFDR | — | [DATA_NEEDED: SFDR dBc at fIN] |
| INL | — | [DATA_NEEDED: INL LSB] |
| DNL | — | [DATA_NEEDED: DNL LSB] |
| Power Dissipation | — | <250 mW at 30 MSPS (typical) |
| Digital Output | — | CMOS, parallel 12-bit |
| Reference | — | Internal (external reference option) |