XC3090L-8PCG84C vs XC3090L-8PC84BKJ Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng XC3090L-8PCG84C sa pamamagitan ng Xilinx at XC3090L-8PC84BKJ sa pamamagitan ng Xilinx. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | XC3090L-8PCG84C | XC3090L-8PC84BKJ |
|---|---|---|
| Brand | Xilinx | Xilinx |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Obsolete |
| Family | XC3000A/L Series FPGA | XC3000L Low-Voltage Logic Cell Array |
| Logic Cells / CLBs | 70 Configurable Logic Blocks | — |
| Gate Count | 6,400 gates (typical) | — |
| Configuration Program Store | 64,160 bits | — |
| User I/O Pins | 70 (maximum) | — |
| Packhaging | 84-pin PLCC (J-Lead, PCG84) | 84-pin PLCC (J-Lead), windowed ceramic (BKJ) |
| Supply Voltage (VCC) | 3.0 V to 3.6 V (low-voltage 'L' variant) | — |
| Speed Grade | -8 (moderate) | -8 (approx. 70 MHz toggle) |
| Temperature na Operasyon | 0 C to +70 C (commercial 'C' suffix) | 0C to +70C (commercial, C suffix) |
| Configuration Modes | Serial master/slave, parallel master/slave, peripheral mode | — |
| Process Technology | [DATA_NEEDED: process node] | 5 ns CMOS SRAM |
| JTAG / Boundary Scan | IEEE 1149.1 compliant | — |
| Configuration Clock Range | [DATA_NEEDED: CCLK frequency range] | — |
| Uri ng Pagpapasok | Surface Mount (PLCC J-Lead) | Through-hole (PLCC socket) |
| Tindminan RoHS | unknown | unknown - legacy windowed ceramic package |
| Lead-Free | unknown | — |
| Level ng MSL | [DATA_NEEDED: MSL rating] | [DATA_NEEDED: MSL rating] |
| Programming Technology | SRAM-based, in-system reconfigurable | — |
| Logic Cells | — | 320 |
| Usable Gates | — | 6,000 |
| Configuration Memory | — | 64,160 bits |
| Maximum User I/O | — | 144 |
| Supply Voltage (Vcc) | — | 3.0 V to 3.6 V (low-voltage) |
| Configuration Method | — | Serial/parallel SRAM, in-system reconfigurable |
| Boundary Scan | — | IEEE 1149.1 (JTAG) compliant |
| Configuration Pins | — | M0, M1, M2 mode-select + DIN, DOUT, CCLK, INIT |