XC6SLX4-2TQG144I vs XC6SLX9-2TQG144I Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng XC6SLX4-2TQG144I sa pamamagitan ng AMD at XC6SLX9-2TQG144I sa pamamagitan ng AMD. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro XC6SLX4-2TQG144I XC6SLX9-2TQG144I
Brand AMD AMD
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Unknown Aktibo
Device Type Spartan-6 LX field-programmable gate array (FPGA) —
Logic Cells 3,840 cells 9,152
Block RAM 221,184 bits 576 Kbits (72 x 18 Kb)
Available I/O 102 pins —
Maksimum na Taktiko ng Oras 375 MHz —
Volte ng Pagbibigay 1.14 V to 1.26 V —
Speed Grade -2 -2 (mid-range)
Packhaging 144-pin TQFP 144-pin TQFP (TQG144), 20 x 20 mm, 0.5 mm pitch
Package Body Size 20 mm x 20 mm —
Package Pitch 0.5 mm —
Process Technology 45 nm 45 nm low-power CMOS (9-metal copper)
Clocking Resources DCM and PLL resources —
Configuration Memory SRAM-type internal latches —
Memory Controller No memory controller in XC6SLX4 —
Temperature Grade Industrial —
Lead-Free Status Lead-free —
Technology CMOS —
Configuration Interface FPGA configuration resources; detailed interface data not provided —
I/O Standard [DATA_NEEDED: supported I/O standards] —
Hanay ng Temperature na Operasyon [DATA_NEEDED: operating temperature range] —
Family — Spartan-6 LX
Slices / ALMs — 1,430 ALMs (715 CLBs)
DSP Slices — 16 (DSP48A1)
Maximum User I/O — 102
Temperature na Operasyon — -40C to +100C (Industrial)
Core Voltage (VCCINT) — 1.2 V
I/O Bank Voltage (VCCO) — 1.2 V to 3.3 V
Memory Interfaces — DDR, DDR2, DDR3, LPDDR (via Memory Controller Block)
Clock Management — DCM + PLL per tile
Uri ng Pagpapasok — Surface Mount
Level ng MSL — 3 (per JEDEC J-STD-020)
Tindminan RoHS — RoHS Compliant (Lead Free)

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