EP910LC-30 vs EP910DC-35 Karşılaştırma

Ayrıntılı yan yana karşılaştırma EP910LC-30 tarafından Altera ve EP910DC-35 tarafından AlteraAnahtar özellikleri, elektriksel parametreleri, ambalajı, yaşam döngüsü durumu, fiyatlandırma ve mevcudiyeti karşılaştırarak tasarım gereksinimleriniz için en iyi bileşeni belirleyin.

Özellik Karşılaştırması

Parametre EP910LC-30 EP910DC-35
Marka Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Yaşam Döngüsü Durumu Obsolete Obsolete
Device Type EPLD (Erasable Programmable Logic Device) UV-Erasable CMOS PLD (PAL-type)
Macrocell Count 24 —
Propagation Delay (tPD) 30 ns (max) —
Maximum Toggle Frequency 62 MHz —
Supply Voltage (VCC) 5 V (nominal, TTL) —
Process Technology CMOS (EPROM-based) —
Package Type PDIP-40 (Plastic DIP, through-hole) —
Operating Temperature Grade Commercial (0C to +70C) —
I/O Pin Count 24 —
Dedicated Input Pins 36 (including I/O) —
Product Terms per Macrocell Up to 16 —
Programming Technology UV-erasable EPROM cell —
Development Tool Altera MAX+PLUS II —
MSL Seviyesi [DATA_NEEDED: MSL level] —
RoHS Durumu [DATA_NEEDED: RoHS status] Non-compliant (ceramic DIP with Pb-bearing lead finish)
Family — Classic EPLD EP910
Architecture — PAL-type sum-of-products AND-OR array
Usable Gates — 900 gates
Macrocells — 24
Product Terms — 240
Dedicated Inputs — 12
I/O Pins — 24
Total Inputs — 36
Propagation Delay (tpd) — 35 ns
Azami Saat Hızı — 37 MHz (typical, internal)
Supply Voltage (Vcc) — 4.75 V to 5.25 V (5 V nominal)
İşletim Sıcaklığı — 0 °C to +70 °C (commercial)
Paket — 40-pin CDIP (Ceramic DIP) with quartz window
Lead Pitch — 2.540 mm
Termination Style — Through-Hole
Programming Method — JEDEC fuse map via device programmer; UV erase
Technology — CMOS, UV-erasable EPROM cell
Lifecycle — Obsolete / last-time-buy from authorized distributors

Dökümanlar & Kaynaklar

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