EPM5192GM vs EPM5192JC-ES Karşılaştırma

Ayrıntılı yan yana karşılaştırma EPM5192GM tarafından Altera ve EPM5192JC-ES tarafından IntelAnahtar özellikleri, elektriksel parametreleri, ambalajı, yaşam döngüsü durumu, fiyatlandırma ve mevcudiyeti karşılaştırarak tasarım gereksinimleriniz için en iyi bileşeni belirleyin.

Özellik Karşılaştırması

Parametre EPM5192GM EPM5192JC-ES
Marka Altera Intel
Kategori FPGA & CPLD FPGA & CPLD
Yaşam Döngüsü Durumu Obsolete Obsolete
Product Family MAX 5000 —
Device Type UV Erasable Programmable Logic Device (PLD) CPLD (EPLD)
Technology CMOS CMOS
Number of Macrocells 192 —
Usable Gates 3,750 —
Pin-to-Pin Delay (tPD) 15 ns (fastest speed grade); 55 ns (this part) —
Counter Frequency (fCNT) up to 76.9 MHz —
Propagation Delay (tPD, this part) 55 ns —
Paket CPGA-84 (Ceramic Pin Grid Array, 84 pins, windowed) 84-pin PLCC (J-lead, CQCC, JEDEC S-CQCC-J84)
Montaj Türü Through-Hole (PGA) Surface Mount
Erasure Method UV (windowed ceramic package) —
Besleme Gerilimi [DATA_NEEDED: typical VCC range] [DATA_NEEDED: VCC nominal]
Maximum User I/O [DATA_NEEDED: exact I/O count for CPGA-84] —
İşletim Sıcaklığı [DATA_NEEDED: commercial/industrial/military grade] [DATA_NEEDED: operating temperature range for ES grade]
RoHS Durumu Non-compliant (contains lead in ceramic PGA) [DATA_NEEDED: RoHS compliance]
Process Node [DATA_NEEDED: CMOS process geometry] —
Programming Interface JTAG-compatible (per MAX 5000 family) —
Device Family — MAX 5000
Macrocells — 192
Logic Array Blocks (LABs) — 12
Interconnect — Programmable Interconnect Array (PIA)
Configuration Memory — EPROM (UV-erasable, one-time programmable for JC-ES)
Programming — Altera MAX+PLUS II or compatible programmer
User I/O Pins — [DATA_NEEDED: user I/O count for JC-ES in PLCC-84]
Lead-Free — [DATA_NEEDED: lead-free status]
MSL Seviyesi — [DATA_NEEDED: MSL rating]
Note — Datasheet source: Altera MAX 5000 family document, 52 pages

Dökümanlar & Kaynaklar

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