EPM5192GM vs EPM5192JC-ES 比較
詳細並排比較 EPM5192GM 由 Altera 與 EPM5192JC-ES 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5192GM | EPM5192JC-ES |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Product Family | MAX 5000 | — |
| Device Type | UV Erasable Programmable Logic Device (PLD) | CPLD (EPLD) |
| Technology | CMOS | CMOS |
| Number of Macrocells | 192 | — |
| Usable Gates | 3,750 | — |
| Pin-to-Pin Delay (tPD) | 15 ns (fastest speed grade); 55 ns (this part) | — |
| Counter Frequency (fCNT) | up to 76.9 MHz | — |
| Propagation Delay (tPD, this part) | 55 ns | — |
| 封裝 | CPGA-84 (Ceramic Pin Grid Array, 84 pins, windowed) | 84-pin PLCC (J-lead, CQCC, JEDEC S-CQCC-J84) |
| 安裝類型 | Through-Hole (PGA) | Surface Mount |
| Erasure Method | UV (windowed ceramic package) | — |
| 供應電壓 | [DATA_NEEDED: typical VCC range] | [DATA_NEEDED: VCC nominal] |
| Maximum User I/O | [DATA_NEEDED: exact I/O count for CPGA-84] | — |
| 工作溫度 | [DATA_NEEDED: commercial/industrial/military grade] | [DATA_NEEDED: operating temperature range for ES grade] |
| RoHS 狀態 | Non-compliant (contains lead in ceramic PGA) | [DATA_NEEDED: RoHS compliance] |
| Process Node | [DATA_NEEDED: CMOS process geometry] | — |
| Programming Interface | JTAG-compatible (per MAX 5000 family) | — |
| Device Family | — | MAX 5000 |
| Macrocells | — | 192 |
| Logic Array Blocks (LABs) | — | 12 |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| Configuration Memory | — | EPROM (UV-erasable, one-time programmable for JC-ES) |
| Programming | — | Altera MAX+PLUS II or compatible programmer |
| User I/O Pins | — | [DATA_NEEDED: user I/O count for JC-ES in PLCC-84] |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| MSL 等級 | — | [DATA_NEEDED: MSL rating] |
| Note | — | Datasheet source: Altera MAX 5000 family document, 52 pages |