EPM9560GC280-20 vs EPM9560R1208-20 Karşılaştırma

Ayrıntılı yan yana karşılaştırma EPM9560GC280-20 tarafından Altera ve EPM9560R1208-20 tarafından AlteraAnahtar özellikleri, elektriksel parametreleri, ambalajı, yaşam döngüsü durumu, fiyatlandırma ve mevcudiyeti karşılaştırarak tasarım gereksinimleriniz için en iyi bileşeni belirleyin.

Özellik Karşılaştırması

Parametre EPM9560GC280-20 EPM9560R1208-20
Marka Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Yaşam Döngüsü Durumu Obsolete Obsolete
Family MAX 9000 MAX 9000
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Usable Gates 12,000 6,000
Macrocells 560 560
Maximum User I/O 212 212
Pin-to-Pin Delay 20 ns (speed grade -20) —
Counter Frequency (max) 100 MHz —
Supply Voltage (VCCINT) 4.75 V to 5.25 V (5.0 V nominal) —
I/O Voltage 3.3 V or 5.0 V configurable —
Process Technology CMOS EEPROM CMOS EEPROM, third-generation MAX architecture
Paket 280-pin CPGA (Ceramic Pin Grid Array) R-1208 (BGA-style fine-pitch)
İşletim Sıcaklığı [DATA_NEEDED: commercial/industrial/military grade] 0C to +70C (commercial)
In-System Programming Yes, via IEEE 1149.1 JTAG —
Montaj Türü Through-Hole (CPGA socket) Surface Mount
RoHS Durumu [DATA_NEEDED: CPGA package historically contains Pb; likely non-compliant] [DATA_NEEDED: confirm via current distributor data]
Logic Array Blocks — 52 (typical for 560 macrocells)
Propagation Delay (tPD) — 20 ns
Maximum Frequency (fMAX) — 125 MHz
Supply Voltage (VCCINT/VCCIO) — 5.0 V
Technology — CMOS EEPROM
In-System Programmability — Yes (IEEE 1149.1 JTAG)
Architecture — Multiple Array MatriX (MAX) with Logic Array Blocks (LABs) and Programmable Interconnect Array (PIA)
Boundary-Scan Test — JTAG IEEE Std. 1149.1
Configuration Memory — On-chip EEPROM (non-volatile)

Dökümanlar & Kaynaklar

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