RTAX1000SL-CGS624V vs RTAX2000SL-CGS624V موازنہ
تفصیلی ساتھ ساتھ موازنہ از RTAX1000SL-CGS624V بذریعہ Microchip Technology اور RTAX2000SL-CGS624V بذریعہ Microchip Technology. اہم خصوصیات، برقی پیرامیٹرز، پیکیجنگ، لائف سائیکل اسٹیٹس، قیمتوں اور دستیابی کا موازنہ کریں تاکہ آپ کی ڈیزائن ضروریات کے لیے بہترین کمپوننٹ کا تعین ہو سکے۔
Microchip Technology
RTAX1000SL-CGS624V - 1M-Gate Rad-Tolerant FPGA | Microchip
RTAX1000SL-CGS624V ✓ فعالMicrochip Technology
RTAX2000SL-CGS624V - 2M-Gate Rad-Tolerant FPGA | Microchip
RTAX2000SL-CGS624V ✓ فعالخصوصیات کا موازنہ
| پیرامیٹر | RTAX1000SL-CGS624V | RTAX2000SL-CGS624V |
|---|---|---|
| برانڈ | Microchip Technology | Microchip Technology |
| زمرہ | FPGA & CPLD | FPGA & CPLD |
| لائف سائیکل کی حالت | فعال | فعال |
| System Gates | 1,000,000 | — |
| Logic Cells | 18144 | — |
| CLBs | 12096 | — |
| Technology | Digital CMOS antifuse | CMOS antifuse (nonvolatile) |
| Family | RTAX-S/SL Radiation-Tolerant FPGAs | RTAX-S/SL Radiation-Tolerant FPGA |
| Programmability | One-Time Programmable (antifuse), live at power-up | — |
| Embedded Memory | Embedded SRAM with built-in FIFO control logic | 540 kbits with optional EDAC protection |
| Clock Resources | Segmentable clocks, chip-wide highway routing | — |
| Carry Logic | Yes (dedicated fast carry chain) | — |
| پیکیج | CGS624 (624-column ceramic grid array) | CG624 ceramic package |
| ماؤنٹنگ ٹائپ | Surface Mount | — |
| Application Domain | Space-flight systems | Space-flight systems |
| Radiation Tolerance | Radiation-tolerant (TID/SEE per manufacturer qualification) | — |
| Max Family Density | 4,000,000 equivalent system gates | — |
| Base Commercial Family | Axcelerator | — |
| آپریٹنگ درجہ حرارت | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| سپلائی وولٹیج | [DATA_NEEDED: core supply voltage] | — |
| Maximum User I/O | [DATA_NEEDED: maximum user I/O count] | — |
| Equivalent System Gates | — | 2000000 |
| Logic Cells (CLBs) | — | 21504 |
| User I/Os (maximum) | — | 684 |
| Total Ionizing Dose (TID) | — | 300 krad (Si) functional / 200 krad (Si) parametric |
| Single-Event Upset Rate | — | Less than 1E-10 errors per bit-day |
| Configuration | — | One-time programmable antifuse, live at power-up |
| Embedded SRAM Features | — | Built-in FIFO control logic |
| Clock Architecture | — | Segmentable clock structures |
| Routing | — | Chip-wide highway routing, carry logic |
| Core Supply Voltage | — | [DATA_NEEDED: core supply voltage] |
| I/O Supply Voltage | — | [DATA_NEEDED: I/O supply voltage] |
| Speed Grade | — | [DATA_NEEDED: speed grade] |
| System Frequency (typical) | — | [DATA_NEEDED: system frequency] |