RTAX1000SL-CGS624V vs RTAX2000SL-CGS624V 比較
詳細並排比較 RTAX1000SL-CGS624V 由 Microchip Technology 與 RTAX2000SL-CGS624V 由 Microchip Technology. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Microchip Technology
RTAX1000SL-CGS624V - 1M-Gate Rad-Tolerant FPGA | Microchip
RTAX1000SL-CGS624V ✓ 啟用中Microchip Technology
RTAX2000SL-CGS624V - 2M-Gate Rad-Tolerant FPGA | Microchip
RTAX2000SL-CGS624V ✓ 啟用中規格比較
| 參數 | RTAX1000SL-CGS624V | RTAX2000SL-CGS624V |
|---|---|---|
| 品牌 | Microchip Technology | Microchip Technology |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | 啟用中 |
| System Gates | 1,000,000 | — |
| Logic Cells | 18144 | — |
| CLBs | 12096 | — |
| Technology | Digital CMOS antifuse | CMOS antifuse (nonvolatile) |
| Family | RTAX-S/SL Radiation-Tolerant FPGAs | RTAX-S/SL Radiation-Tolerant FPGA |
| Programmability | One-Time Programmable (antifuse), live at power-up | — |
| Embedded Memory | Embedded SRAM with built-in FIFO control logic | 540 kbits with optional EDAC protection |
| Clock Resources | Segmentable clocks, chip-wide highway routing | — |
| Carry Logic | Yes (dedicated fast carry chain) | — |
| 封裝 | CGS624 (624-column ceramic grid array) | CG624 ceramic package |
| 安裝類型 | Surface Mount | — |
| Application Domain | Space-flight systems | Space-flight systems |
| Radiation Tolerance | Radiation-tolerant (TID/SEE per manufacturer qualification) | — |
| Max Family Density | 4,000,000 equivalent system gates | — |
| Base Commercial Family | Axcelerator | — |
| 工作溫度 | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| 供應電壓 | [DATA_NEEDED: core supply voltage] | — |
| Maximum User I/O | [DATA_NEEDED: maximum user I/O count] | — |
| Equivalent System Gates | — | 2000000 |
| Logic Cells (CLBs) | — | 21504 |
| User I/Os (maximum) | — | 684 |
| Total Ionizing Dose (TID) | — | 300 krad (Si) functional / 200 krad (Si) parametric |
| Single-Event Upset Rate | — | Less than 1E-10 errors per bit-day |
| Configuration | — | One-time programmable antifuse, live at power-up |
| Embedded SRAM Features | — | Built-in FIFO control logic |
| Clock Architecture | — | Segmentable clock structures |
| Routing | — | Chip-wide highway routing, carry logic |
| Core Supply Voltage | — | [DATA_NEEDED: core supply voltage] |
| I/O Supply Voltage | — | [DATA_NEEDED: I/O supply voltage] |
| Speed Grade | — | [DATA_NEEDED: speed grade] |
| System Frequency (typical) | — | [DATA_NEEDED: system frequency] |