ADC1613D125HN-C1 - Dual 16-Bit 125MSPS ADC, JESD204A | Renesas
MPN: ADC1613D125HN-C1 ✓ Hoạt độngADC1613D125HN-C1 Tóm tắt
A pipelined ADC (pipelined analog-to-digital converter) is a high-speed converter architecture that uses multiple cascaded low-resolution flash stages to digitize analog signals at sample rates from a few MSPS to several hundred MSPS. Pipelined ADCs sit in the data-converter hierarchy between successive-approximation register (SAR) ADCs (typically <10 MSPS, very low power) and flash ADCs (GHz-class but high power, low resolution). They are the workhorse converters for communications infrastructure, radar, test equipment, and medical imaging where high SFDR and wide input bandwidth are required simultaneously.
Key features include 16-bit resolution per channel, 65/80/105/125 MSPS programmable sampling rates per channel, 80000-sample-per-second per-channel minimum guaranteed throughput, JESD204A subclass 0/1 compliant serial output supporting up to 3.125 Gbps lane rates, and on-chip clock divider with deterministic latency. The HVQFN-56 package with exposed pad delivers a compact 8x8 mm footprint while providing low thermal resistance for sustained multi-channel operation in dense PCB layouts. Industrial temperature range of -40 C to +85 C supports outdoor and industrial deployments.
The device accepts differential analog inputs with 1.5 Vpp full-scale range and includes dither, gain, offset, and phase calibration registers for per-channel SFDR optimization across process and temperature variations. Internal voltage reference stability reduces board area and BOM cost versus designs requiring external precision references. Power consumption scales with sample rate, allowing the same converter to be reused across multiple product platforms.
Typical applications include multi-standard software-defined radio receivers, LTE and 5G NR base-station observation receivers, radar digitizers, ultrasound beamforming front-ends, and automated test equipment digitizers. The JESD204A interface minimizes board routing by serializing 16-bit data lanes onto one or two high-speed differential pairs, freeing FPGA pins for additional channels or processing functions.
When designing with this ADC, designers should follow JESD204A link-layer setup guidelines to achieve deterministic latency and maintain the specified SFDR. The exposed pad must be soldered to a continuous ground plane for thermal and signal-integrity performance.
This page synthesizes distributor pricing, drop-in same-package alternatives, application companions, and practical design notes that complement, but do not substitute for, the official Renesas datasheet.
Bộ thay thế dễ dàng lắp đặt cho ADC1613D125HN-C1 — cùng gói, chân-to-chân tương thích. Các bộ phận yêu cầu hàn PCB bị loại trừ.
Các biến thể trong loạt này
Các mẫu cùng loạt có thể lắp đặt dễ dàng tương thích với ADC1613D125HN-C1 (cùng hình factor và footprint) — khác nhau ở Package, Operating Temperature, Number of Channels, Output Interface, Manufacturer.
ADC1613D125HN/C1,5
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
ADC1613D105HN-C1
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →ADC1613D080HN-C1
✅ Drop-In ⚠️ Thông số chưa được xác minhLiên hệ để biết giá
Xem tài liệu →ADC1610S125HN-C1
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →ADC1213S125HN-C1
✅ Drop-In ⚠️ Thông số chưa được xác minhLiên hệ để biết giá
Xem tài liệu →AD9268XCPZ-125
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →ADC1613D125HN-C1 Tỷ lệ tối đa & tính chất điện
| Độ phân giải | 16 bit |
| Number of Channels | 2 |
| Architecture | Pipelined |
| Sample Rate (max) | 125 MSPS |
| Programmable Sample Rates | 65 / 80 / 105 / 125 MSPS |
| Minimum Guaranteed Sample Rate | 80 kSPS |
| Output Interface | JESD204A (serial) |
| JESD204A Subclass | 0 / 1 |
| JESD204A Lane Rate (max) | 3.125 Gbps |
| Analog Input Type | Differential |
| Full-Scale Input Range | 1.5 Vpp (differential) |
| Voltage Reference | Internal |
| Hộp | 56-HVQFN (8x8 mm, SOT684-7) with exposed pad |
| Nhiệt độ hoạt động | -40 C to +85 C (industrial) |
| Screening Level | Industrial |
| Trạng thái RoHS | Compliant |
| Số chân | 56 |
Cấu hình chân ADC1613D125HN-C1
| Chân 1 | VA1VDD — Analog 1 supply voltage |
| Chân 2 | VA1GND — Analog 1 ground |
| Chân 3 | INA_P — Channel A positive analog input |
| Chân 4 | INA_N — Channel A negative analog input |
| Chân 5 | VA1VDD — Analog 1 supply voltage |
| Chân 6 | VA1GND — Analog 1 ground |
| Chân 7 | INB_P — Channel B positive analog input |
| Chân 8 | INB_N — Channel B negative analog input |
| Chân 9 | VA1VDD — Analog 1 supply voltage |
| Chân 10 | VA1GND — Analog 1 ground |
| Chân 11 | CM_OUT — Common-mode voltage output |
| Chân 12 | VREF — Voltage reference decoupling |
| Chân 13 | VA2VDD — Analog 2 supply voltage |
| Chân 14 | VA2GND — Analog 2 ground |
| Chân 15 | CLK_P — Sample clock positive input |
| Chân 16 | CLK_N — Sample clock negative input |
| Chân 17 | VA2VDD — Analog 2 supply voltage |
| Chân 18 | VA2GND — Analog 2 ground |
| Chân 19 | NC — Not connected (per datasheet) |
| Chân 20 | SENSE — Reference sense pin |
| Chân 21 | VD1VDD — Digital 1 supply voltage |
| Chân 22 | VD1GND — Digital 1 ground |
| Chân 23 | RESET — Hardware reset (active low) |
| Chân 24 | PDN — Power-down (active high) |
| Chân 25 | CSB — SPI chip select (active low) |
| Chân 26 | SCLK — SPI serial clock |
| Chân 27 | SDIO — SPI serial data I/O |
| Chân 28 | SDO — SPI serial data output |
| Chân 29 | VD1VDD — Digital 1 supply voltage |
| Chân 30 | VD1GND — Digital 1 ground |
| Chân 31 | SYNC_P — JESD204A sync positive |
| Chân 32 | SYNC_N — JESD204A sync negative |
| Chân 33 | VD2VDD — Digital 2 supply voltage |
| Chân 34 | VD2GND — Digital 2 ground |
| Chân 35 | OUT0_P — JESD204A lane 0 positive output |
| Chân 36 | OUT0_N — JESD204A lane 0 negative output |
| Chân 37 | VD2VDD — Digital 2 supply voltage |
| Chân 38 | VD2GND — Digital 2 ground |
| Chân 39 | OUT1_P — JESD204A lane 1 positive output |
| Chân 40 | OUT1_N — JESD204A lane 1 negative output |
| Chân 41 | VD2VDD — Digital 2 supply voltage |
| Chân 42 | VD2GND — Digital 2 ground |
| Chân 43 | NC — Not connected (per datasheet) |
| Chân 44 | NC — Not connected (per datasheet) |
| Chân 45 | NC — Not connected (per datasheet) |
| Chân 46 | TEST — Test mode (factory use) |
| Chân 47 | NC — Not connected (per datasheet) |
| Chân 48 | NC — Not connected (per datasheet) |
| Chân 49 | NC — Not connected (per datasheet) |
| Chân 50 | NC — Not connected (per datasheet) |
| Chân 51 | NC — Not connected (per datasheet) |
| Chân 52 | VD3VDD — Digital 3 supply voltage |
| Chân 53 | VD3GND — Digital 3 ground |
| Chân 54 | NC — Not connected (per datasheet) |
| Chân 55 | NC — Not connected (per datasheet) |
| Chân 56 | EP — Exposed thermal pad - connect to ground |
Ứng dụng tiêu biểu
ADC1613D125HN-C1 phù hợp cho 6 Áp dụngs: Software-Defined Radio (SDR) Receiver, LTE / 5G NR Base Station Observation Receiver, Radar and Lidar Digitizer Front-End, Ultrasound Beamforming Receiver, Automated Test Equipment (ATE) Digitizer, Spectrum Analyzer and Signal Intelligence.
Software-Defined Radio (SDR) Receiver
The ADC1613D125HN-C1 is well suited to wideband SDR receiver front-ends where 16-bit resolution directly improves demodulation SNR across multi-carrier signals. Its dual-channel architecture supports two diversity or MIMO digitizer paths from a single converter, while the JESD204A interface routes data over a single high-speed lane to the host FPGA at up to 3.125 Gbps - eliminating 16+ parallel LVDS pairs per channel. The 125 MSPS per-channel sample rate covers IF sampling up to ~62.5 MHz, matching common SDR IF frequencies. Industrial -40 C to +85 C operation supports outdoor tactical and commercial radio deployments. Designers can pair this ADC with XAIPART-listed companion parts such as clock jitter cleaners and FPGA transceivers.
Được đề xuất
LTE / 5G NR Base Station Observation Receiver
In LTE and 5G NR base-station observation receivers, the ADC1613D125HN-C1 digitizes two antenna paths at 125 MSPS with 16-bit dynamic range, providing sufficient SFDR for multi-carrier signal analysis at the radio unit. The JESD204A subclass 1 mode delivers deterministic latency required for downlink observation, while the internal voltage reference minimizes board area versus designs requiring external precision references. The HVQFN-56 (8x8 mm) footprint suits compact RRH and small-cell radio units where PCB real estate is at a premium. Industrial temperature rating supports outdoor tower-top deployment without additional thermal management. For lower-speed variants in the same family, see ADC1613D105HN-C1 also listed on XAIPART.
Được đề xuất
Radar and Lidar Digitizer Front-End
The ADC1613D125HN-C1 dual-channel 125 MSPS sampling makes it a strong fit for radar and lidar digitizer front-ends, where I/Q baseband or dual-antenna signals require simultaneous sampling with matched gain and phase. The 16-bit resolution captures low-amplitude return signals without saturating on clutter, while the pipelined architecture delivers the SFDR needed to separate small targets from large nearby reflectors. The JESD204A interface links directly to FPGA transceivers used in radar DSP pipelines, and the HVQFN-56 exposed pad provides thermal headroom for sustained multi-channel operation. Designers commonly pair this ADC with FPGA-based beamforming and FFT processing blocks for SAR and FMCW radar designs.
Được đề xuất
Ultrasound Beamforming Receiver
Medical ultrasound beamforming receivers benefit from the ADC1613D125HN-C1's dual-channel, 16-bit, 125 MSPS architecture for digitizing phased-array transducer channels at IF frequencies up to ~62.5 MHz. The two channels per package reduce PCB area in dense probe-head and beamformer-board designs, and the JESD204A serial interface lowers FPGA pin count compared to parallel LVDS, freeing pins for additional receive channels. Low power dissipation plus the HVQFN-56 thermal pad support the multi-channel density required for 64-256 element arrays. Industrial temperature grade accommodates clinical and portable ultrasound cart environments.
Được đề xuất
Automated Test Equipment (ATE) Digitizer
In automated test equipment digitizers, the ADC1613D125HN-C1 captures two simultaneous test channels at 125 MSPS with 16-bit resolution, enabling wide dynamic range measurements of mixed-signal DUTs. The internal calibration registers (gain, offset, phase) help maintain SFDR across long calibration intervals typical of production test floors. JESD204A output interfaces to FPGA-based DSP for inline FFT and statistical analysis, accelerating test throughput. The 56-HVQFN footprint supports high-channel-count PXI/AXIe instruments. Designers can reference the Renesas datasheet calibration procedure for per-channel SFDR optimization at production test.
Được đề xuất
Spectrum Analyzer and Signal Intelligence
Spectrum analyzer and signal-intelligence front-ends use the ADC1613D125HN-C1's dual 16-bit, 125 MSPS capability to capture wide instantaneous bandwidths while maintaining high SFDR for weak-signal detection. The differential 1.5 Vpp input range accommodates direct IF sampling of HF/VHF/UHF signals, and the internal voltage reference simplifies calibration across production units. JESD204A subclass 1 deterministic latency supports time-coherent multi-board array processing required by direction-finding systems. Industrial -40 C to +85 C operation covers field-deployable signal-intelligence platforms. For lower-bandwidth segments, the same ADC can be clocked at 65 or 80 MSPS to reduce power.
Được đề xuất
Tóm tắt các sản phẩm được đề xuất
Dữ liệu tham khảo kỹ thuật cho ADC1613D125HN-C1 — so sánh, hướng dẫn thiết kế và thông tin tuân thủ.
Hướng dẫn chọn lựa
So sánh với các sản phẩm thay thế
| Tham số | Sản phẩm này | ADC1613D125HN/C1,5 | ADC1613D105HN-C1 | ADC1613D080HN-C1 | ADC1610S125HN-C1 | AD9268XCPZ-125 |
|---|---|---|---|---|---|---|
| Brand | Renesas Electronics | Renesas Electronics (legacy NXP/IDT code) | Renesas Electronics | Renesas Electronics | Renesas Electronics | Analog Devices |
| Package | 56-HVQFN (8x8 mm) | 56-HVQFN (8x8 mm) - same | 56-HVQFN (8x8 mm) - same | 56-HVQFN (8x8 mm) - same | 56-HVQFN (8x8 mm) - same | LFCSP/QFN-56 (pinout verification required) |
| Resolution | 16 bit | 16 bit | 16 bit | 16 bit | 16 bit | 16 bit |
| Channels | 2 | 2 | 2 | 2 | 1 | 2 |
| Max Sample Rate | 125 MSPS | 125 MSPS | 105 MSPS | 80 MSPS | 125 MSPS | 125 MSPS |
| Output Interface | JESD204A | JESD204A | JESD204A | JESD204A | JESD204A | JESD204A |
Bảo phân biệt quan trọng
- Dual 16-bit 125 MSPS with JESD204A in compact 8x8 mm HVQFN (vsADC1613D105HN-C1)
- Dual-channel architecture in same package (vsADC1610S125HN-C1)
- Highest 16-bit resolution in the family (vsADC1213S125HN-C1)
- Internal voltage reference eliminates external reference IC (vsAD9268XCPZ-125)
Ghi chú thiết kế
The HVQFN-56 exposed thermal pad MUST be soldered to a continuous, unbroken ground plane directly beneath the IC. Use an array of thermal vias (0.3 mm drill, 0.6 mm pitch, 9-13 vias minimum) under the pad to stitch the top-side ground pour to inner ground planes. Per the Renesas datasheet, this thermal path is essential for sustained dual-channel operation at 125 MSPS and prevents thermal-shutdown events in high-ambient-temperature enclosures.
Route the differential analog inputs (INA_P/INA_N, INB_P/INB_N) and the differential sample clock (CLK_P/CLK_N) as 100-ohm differential transmission lines with matched length within each pair. Keep the analog input traces short and isolated from the JESD204A digital outputs (OUT0_P/N, OUT1_P/N) to minimize digital noise coupling into the analog front-end. The Renesas datasheet reference layout shows a guard ring around the analog inputs connected to VAxGND.
Decouple each VA1VDD, VA2VDD, VD1VDD, VD2VDD, and VD3VDD pin with a 100 nF X7R ceramic capacitor placed as close as possible to the pin, plus a 10 uF bulk capacitor on each supply rail. Estimated: assuming dual-channel operation at 125 MSPS the total supply current is in the order of ~300 mA across all rails. Use ferrite beads between analog and digital supply domains to prevent digital switching noise from coupling into the analog reference.
Do not omit the CM_OUT common-mode bypass capacitor - the ADC's internal biasing depends on it for proper input common-mode voltage. JESD204A subclass 1 deterministic latency requires careful PCB trace-length matching between the FPGA transceiver reference clock and the SYNC_P/SYNC_N pair; mismatches >2 mm can break link initialization. Always run the on-chip calibration routine after final PCB assembly to recover per-channel gain/offset/phase SFDR performance.
Thông tin tuân thủ
RoHS compliance per Verified Web Data listing on Mouser/DigiKey for ADC1613D125HN-C1. Industrial temperature grade only; AEC-Q100 automotive grade not available for this part number.
