ADS62P28IRGC25 - Dual 12-Bit 210-MSPS ADC with DDR LVDS/CMOS | TI
MPN: ADS62P28IRGC25 ✓ Hoạt độngADS62P28IRGC25 Tóm tắt
An analog-to-digital converter is a mixed-signal integrated circuit that converts continuous-time analog voltages into discrete digital codes at a specified sampling rate. High-speed ADCs such as the ADS62P28 sit at the boundary between the analog front-end (amplifiers, filters, baluns) and the digital back-end (FPGAs, ASICs, DSPs). The 12-bit 210-MSPS class is commonly deployed in communications infrastructure, medical imaging, and industrial test equipment where cost-effective quantization of IF/RF signals is required.
Key features include dual-channel sampling up to 210 MSPS, selectable DDR LVDS or parallel CMOS outputs, programmable full-scale input range, internal dither for spurious-free dynamic range (SFDR) improvement, and a low-jitter clock buffer with divide-by-2/4 options. The pipelined architecture provides low latency (typically 3-4 clock cycles) and excellent linearity across the operating temperature range. The 64-VQFN package with exposed thermal pad supports the 1.7 W typical power dissipation with standard PCB thermal design.
The ADS62P28 uses a switched-capacitor pipelined core with on-chip reference, supporting single-ended or differential analog inputs with up to 2 Vpp full-scale. The digital output stage can be configured for either LVDS (for high-speed serial data transfer to an FPGA) or parallel CMOS (for direct connection to lower-speed digital ASICs). Built-in digital features include programmable gain, offset correction, and a test-pattern generator for board-level bring-up.
Typical applications include wireless communications receivers (LTE, WCDMA, multi-carrier GSM base stations), cable infrastructure (DVB-SC, DOCSIS downstream/upstream), radar and electronic-warfare intermediate-frequency digitizers, medical ultrasound beamformers, and high-speed data acquisition for industrial test and measurement. The dual-channel architecture enables I/Q or diversity reception in a single chip.
When designing with this part, ensure the analog input common-mode voltage and clock jitter budget meet the SNR specification. Use the exposed thermal pad with adequate copper area for heat removal, and place decoupling capacitors as close as possible to the supply pins.
This page synthesizes distributor pricing, drop-in alternatives from TI's ADS62Pxx family, and practical design notes not found in the manufacturer datasheet.
Bộ thay thế dễ dàng lắp đặt cho ADS62P28IRGC25 — cùng gói, chân-to-chân tương thích. Các bộ phận yêu cầu hàn PCB bị loại trừ.
Các biến thể trong loạt này
Các mẫu cùng loạt có thể lắp đặt dễ dàng tương thích với ADS62P28IRGC25 (cùng hình factor và footprint) — khác nhau ở Input Type, Package, Output Interface, Architecture, Number of Channels.
ADS62P29IRGC25
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
ADS62P28IRGCT
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
ADS62P25IRGC25
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →ADS62P48IRGC25
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →ADS62P23IRGC25
✅ Drop-In ⚠️ Thông số chưa được xác minhLiên hệ để biết giá
Xem tài liệu →ADS62P22IRGC25
✅ Drop-In ⚠️ Thông số chưa được xác minhLiên hệ để biết giá
Xem tài liệu →ADS62P28IRGC25 Tỷ lệ tối đa & tính chất điện
| Độ phân giải | 12 bit |
| Number of Channels | 2 (dual) |
| Tỷ lệ lấy mẫu | 210 MSPS |
| Architecture | Pipelined |
| Input Type | Differential / Single-ended |
| Full-Scale Input Range | 1 Vpp to 2 Vpp (programmable) |
| Output Interface | DDR LVDS / Parallel CMOS (selectable) |
| SNR | 70 dBFS (typical at 70 MHz IF) |
| SFDR | 85 dBc (typical at 70 MHz IF) |
| Analog Supply Voltage | 3.3 V |
| Digital Supply Voltage | 1.8 V (LVDS mode) |
| Power Dissipation | 1.7 W typical |
| Input Bandwidth | 450 MHz (3 dB) |
| Hộp | 64-VQFN (RGC) 9x9 mm with exposed pad |
| Nhiệt độ hoạt động | -40 C to +85 C (Industrial) |
| Trạng thái RoHS | Compliant |
Cấu hình chân ADS62P28IRGC25
| Chân 1 | INB1P — Channel B analog input positive |
| Chân 2 | INB1N — Channel B analog input negative |
| Chân 3 | VCM — Common-mode voltage output |
| Chân 4 | INA1P — Channel A analog input positive |
| Chân 5 | INA1N — Channel A analog input negative |
| Chân 6 | AVDD3V — Analog 3.3 V supply |
| Chân 7 | AVDD3V — Analog 3.3 V supply |
| Chân 8 | AGND — Analog ground |
| Chân 9 | AVDD1V8 — Analog 1.8 V supply |
| Chân 10 | REFT — Internal reference top |
| Chân 11 | REFB — Internal reference bottom |
| Chân 12 | REFCAP — Reference decoupling |
| Chân 13 | AGND — Analog ground |
| Chân 14 | CLKP — Clock input positive |
| Chân 15 | CLKN — Clock input negative |
| Chân 16 | AVDD3V — Analog 3.3 V supply |
| Chân 17 | AGND — Analog ground |
| Chân 18 | SCLK — Serial programming clock |
| Chân 19 | SDATA — Serial programming data |
| Chân 20 | SEN — Serial programming enable |
| Chân 21 | RESET — Hardware reset (active low) |
| Chân 22 | PDN — Power down (active high) |
| Chân 23 | DRVDD — Digital driver supply |
| Chân 24 | DGND — Digital ground |
| Chân 25 | DA0P — Channel A LVDS data output 0+ |
| Chân 26 | DA0N — Channel A LVDS data output 0- |
| Chân 27 | DA1P — Channel A LVDS data output 1+ |
| Chân 28 | DA1N — Channel A LVDS data output 1- |
| Chân 29 | DA2P — Channel A LVDS data output 2+ |
| Chân 30 | DA2N — Channel A LVDS data output 2- |
| Chân 31 | DA3P — Channel A LVDS data output 3+ |
| Chân 32 | DA3N — Channel A LVDS data output 3- |
| Chân 33 | DA4P — Channel A LVDS data output 4+ |
| Chân 34 | DA4N — Channel A LVDS data output 4- |
| Chân 35 | DA5P — Channel A LVDS data output 5+ |
| Chân 36 | DA5N — Channel A LVDS data output 5- |
| Chân 37 | DRVDD — Digital driver supply |
| Chân 38 | DGND — Digital ground |
| Chân 39 | DB0P — Channel B LVDS data output 0+ |
| Chân 40 | DB0N — Channel B LVDS data output 0- |
| Chân 41 | DB1P — Channel B LVDS data output 1+ |
| Chân 42 | DB1N — Channel B LVDS data output 1- |
| Chân 43 | DB2P — Channel B LVDS data output 2+ |
| Chân 44 | DB2N — Channel B LVDS data output 2- |
| Chân 45 | DB3P — Channel B LVDS data output 3+ |
| Chân 46 | DB3N — Channel B LVDS data output 3- |
| Chân 47 | DB4P — Channel B LVDS data output 4+ |
| Chân 48 | DB4N — Channel B LVDS data output 4- |
| Chân 49 | DB5P — Channel B LVDS data output 5+ |
| Chân 50 | DB5N — Channel B LVDS data output 5- |
| Chân 51 | DRVDD — Digital driver supply |
| Chân 52 | DGND — Digital ground |
| Chân 53 | CLKDIVP — Clock divided LVDS+ |
| Chân 54 | CLKDIVN — Clock divided LVDS- |
| Chân 55 | DRVDD — Digital driver supply |
| Chân 56 | DGND — Digital ground |
| Chân 57 | NC — Not connected |
| Chân 58 | NC — Not connected |
| Chân 59 | OUTMODE — Output mode select (LVDS/CMOS) |
| Chân 60 | AVDD1V8 — Analog 1.8 V supply |
| Chân 61 | AVDD3V — Analog 3.3 V supply |
| Chân 62 | AGND — Analog ground |
| Chân 63 | REF — Reference select |
| Chân 64 | AVDD1V8 — Analog 1.8 V supply |
| Chân 65 | DAP — Exposed thermal pad (bottom) |
Ứng dụng tiêu biểu
ADS62P28IRGC25 phù hợp cho 6 Áp dụngs: LTE / WCDMA Base Station IF Sampling, Cable Infrastructure / DOCSIS Downstream, Medical Ultrasound Beamforming, Radar / Electronic Warfare IF Digitization, Test & Measurement Instrumentation, Industrial High-Speed Data Acquisition.
LTE / WCDMA Base Station IF Sampling
The ADS62P28IRGC25's dual 210-MSPS 12-bit conversion with 70 dBFS SNR and 85 dBc SFDR makes it well-suited for multi-carrier LTE and WCDMA base-station IF chains. Per TI's datasheet, two on-chip ADC cores handle independent I/Q or diversity paths simultaneously, eliminating the need for two discrete ADC ICs in a single-board radio. The DDR LVDS output streams up to 420 MSPS aggregate data into an FPGA or ASIC for downstream channelization. Compared with 14-bit alternatives, the 12-bit ADS62P28 provides adequate quantization for legacy 3G/4G receivers while consuming only 1.7 W typical - well within the thermal envelope of compact remote-radio-head designs.
Được đề xuất
Cable Infrastructure / DOCSIS Downstream
In cable-headend downstream digitizers, the ADS62P28IRGC25 samples IF outputs from QAM modulators at up to 210 MSPS, supporting DOCSIS 3.0/3.1 channel plans. According to the TI ADS62P28 datasheet, the dual-channel architecture enables capture of two independent downstream bands with a single chip, while the selectable DDR LVDS or parallel CMOS outputs simplify integration with cable-modem-termination-system (CMTS) ASICs. The internal reference and programmable 1-2 Vpp full-scale input range handle the wide dynamic range of aggregated QAM carriers without external level-shifting hardware.
Được đề xuất
Medical Ultrasound Beamforming
The ADS62P28IRGC25 is widely deployed in medical ultrasound front-end receivers, digitizing each transducer channel's echo return at rates up to 210 MSPS. Per TI's application information, the dual-channel pipelined architecture provides low-latency conversion essential for time-gain-compensation and beamforming pipelines, while the high SFDR (>85 dBc) preserves subtle tissue-contrast signals. The 64-VQFN package's small 9x9 mm footprint enables high channel density on ultrasound probe-interface boards, where dozens of channels must fit within a compact cable connector envelope.
Được đề xuất
Radar / Electronic Warfare IF Digitization
Defense and aerospace IF-sampling radar systems use the ADS62P28IRGC25 to digitize wideband intermediate-frequency signals from radar front-ends. According to TI's datasheet, the 450 MHz analog input bandwidth supports sub-sampling of IF bands up to 200 MHz with alias-protected Nyquist capture, while the dual channels enable simultaneous sum-and-difference channel digitization for monopulse radar. The industrial -40C to +85C temperature range accommodates the thermal environment of outdoor or vehicular radar installations.
Được đề xuất
Test & Measurement Instrumentation
High-end oscilloscopes, spectrum analyzers, and arbitrary-waveform-digitizers use the ADS62P28IRGC25 as a 12-bit digitizer for transient capture and signal analysis. Per TI's datasheet, the pipelined architecture's 3-4 clock-cycle latency is well-suited for trigger-and-capture workflows, and the selectable DDR LVDS output allows streaming to deep-memory FPGAs at full 210 MSPS. Combined with the part's 70 dBFS SNR, this ADC delivers an effective number of bits (ENOB) of approximately 11.3 at low input frequencies, adequate for general-purpose lab equipment.
Được đề xuất
Industrial High-Speed Data Acquisition
Industrial process control, vibration monitoring, and power-quality analysis deploy the ADS62P28IRGC25 for synchronized multi-channel sampling of sensor arrays. According to TI's datasheet, the dual-channel pipelined ADC with programmable full-scale input range (1-2 Vpp) accommodates a wide range of industrial sensors (accelerometers, current shunts, strain gauges) without external attenuators. The CMOS-parallel output mode simplifies connection to lower-cost industrial microcontrollers for embedded data loggers where the LVDS interface is not required.
Được đề xuất
Tóm tắt các sản phẩm được đề xuất
Dữ liệu tham khảo kỹ thuật cho ADS62P28IRGC25 — so sánh, hướng dẫn thiết kế và thông tin tuân thủ.
Hướng dẫn chọn lựa
So sánh với các sản phẩm thay thế
| Tham số | Sản phẩm này | ADS62P29IRGC25 | ADS62P28IRGCT | ADS62P25IRGC25 | ADS62P48IRGC25 | ADS62P23IRGC25 |
|---|---|---|---|---|---|---|
| Package | 64-VQFN (RGC) 9x9 mm | 64-VQFN (RGC) 9x9 mm - same | 64-VQFN (RGC) 9x9 mm - same | 64-VQFN (RGC) 9x9 mm - same | 64-VQFN (RGC) 9x9 mm - same | 64-VQFN (RGC) 9x9 mm - same |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Resolution | 12 bit | 14 bit | 12 bit | 12 bit | 14 bit | 12 bit |
| Sampling Rate | 210 MSPS | 210 MSPS | 210 MSPS | 170 MSPS | 210 MSPS | 80 MSPS |
| Number of Channels | 2 | 2 | 2 | 2 | 2 | 2 |
| SNR (typ, 70 MHz IF) | 70 dBFS | ~72 dBFS | 70 dBFS | 70 dBFS | ~72 dBFS | 70 dBFS |
| Output Interface | DDR LVDS / CMOS | DDR LVDS / CMOS | DDR LVDS / CMOS | DDR LVDS / CMOS | DDR LVDS / CMOS | DDR LVDS / CMOS |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
Bảo phân biệt quan trọng
- Higher sampling rate than ADS62P25 at same 12-bit resolution (vsADS62P25IRGC25)
- Identical pinout and digital interface across the ADS62Pxx family (vsADS62P29IRGC25)
- Integrated dual channels reduce board area (vsADS58C28 (single-channel alternatives))
Ghi chú thiết kế
Estimated: at 1.7 W typical dissipation in a 64-VQFN package, junction-to-ambient thermal resistance (theta_JA) is approximately 25 C/W on a 4-layer JEDEC test board. This yields a junction temperature rise of ~43C above ambient at full output rate, leaving margin to the 125C junction limit. For reliable operation at sustained 210 MSPS, solder the exposed thermal pad (pin 65 / DAP) directly to a copper pour of at least 1 square inch on the top layer, with thermal vias to internal ground planes.
The ADS62P28 requires two analog supplies (AVDD3V = 3.3 V for the analog front-end, AVDD1V8 = 1.8 V for the pipelined cores) and one digital driver supply (DRVDD = 1.8 V in LVDS mode). According to the TI datasheet, place 0.1 uF ceramic decoupling capacitors as close as possible to each supply pin, with a 10 uF bulk tantalum or ceramic capacitor on each supply rail to filter low-frequency noise. Star-ground the analog (AGND) and digital (DGND) returns at a single point under the exposed pad.
For clock integrity, drive CLKP/CLKN with a low-jitter differential source (typically <300 fs RMS jitter for full SNR). According to the TI ADS62P28 datasheet, the analog input bandwidth is 450 MHz; use a balanced, 100-ohm differential trace layout from the front-end balun/amplifier to the INA1P/N or INB1P/N pins. Keep the analog input traces short and symmetric to preserve common-mode rejection and minimize second-harmonic distortion.
The 64-VQFN package with exposed thermal pad requires proper PCB design for both electrical and thermal performance. Use a 9x9 mm land pattern with the central exposed pad exposed on the top layer (no solder mask) and an array of thermal vias (typically 0.3 mm diameter, 1 mm pitch) connecting to internal ground planes. Per TI's packaging guidelines, avoid routing signals beneath the package body and keep all high-speed LVDS traces length-matched within 1 mm to preserve DDR timing margins.
Common design pitfalls include: (1) leaving the exposed thermal pad unsoldered, leading to thermal overheating and SNR degradation; (2) failing to program the internal register map via SCLK/SDATA/SEN before operation - the device defaults to a safe state but must be configured for full performance; (3) using CMOS output mode when the downstream FPGA cannot accept DDR data rates - in this case, use LVDS mode with a 100-ohm termination at the receiver. Refer to TI's ADS62P28 datasheet register map for the correct power-up sequence.
Thông tin tuân thủ
RoHS and REACH compliant per TI product page. Industrial temperature grade only - not AEC-Q100 qualified for automotive applications.
