CGD65A130SH2 - 650V GaN HEMT 12A 55mΩ ICeGaN | Cambridge GaN Devices
MPN: CGD65A130SH2 ✓ Hoạt độngCGD65A130SH2 Tóm tắt
A GaN HEMT (Gallium Nitride High Electron Mobility Transistor) is a wide-bandgap power transistor that uses an AlGaN/GaN heterostructure to form a two-dimensional electron gas (2DEG) channel. Compared with silicon MOSFETs, GaN HEMTs offer dramatically lower output capacitance, near-zero reverse-recovery charge, and switching speeds in the MHz range, making them suited for high-frequency, high-density power conversion. The CGD65A130SH2 sits in the power-management hierarchy as a discrete GaN switch used as the main power element in high-frequency switched-mode power supplies (SMPS), motor drives, and photovoltaic inverters.
Key features of the CGD65A130SH2 include 650 V drain-source breakdown, 55 mΩ typical R_DS(on), ICeGaN® compatibility with standard 5 V gate drivers, integrated current-sense (CS) pin, and the NL³ (Non-Linear Loss Limiting) circuit that maintains low drive losses even at very high switching frequencies. The wide gate-threshold window and built-in current sensing simplify layout by reducing the need for external shunt resistors and isolated gate-drive bias supplies.
Typical application circuits include 65 W to 500 W USB-PD chargers, totem-pole PFC (power factor correction) front ends for server and telecom rectifiers, half-bridge LLC and quasi-resonant converters for high-density AC/DC adapters, photovoltaic micro-inverters, and motor-drive half-bridges. The integrated current-sense output also enables cycle-by-cycle current limiting and over-current protection without an external shunt.
This page synthesises distributor pricing, distributor stock, drop-in alternatives analysis, and CGD reference-design guidance that complement the manufacturer datasheet. When designing with CGD65A130SH2, ensure the gate-driver pull-up meets the ICeGaN® gate-charging requirements and that the PCB returns have low inductance to control ringing in the MHz switching range. The 16-DFN exposed pad must be soldered to a sufficient copper pour to keep R_DS(on) stable and junction temperature within rated limits.
Bộ thay thế dễ dàng lắp đặt cho CGD65A130SH2 — cùng gói, chân-to-chân tương thích. Các bộ phận yêu cầu hàn PCB bị loại trừ.
Các biến thể trong loạt này
Các mẫu cùng loạt có thể lắp đặt dễ dàng tương thích với CGD65A130SH2 (cùng hình factor và footprint) — khác nhau ở Package, Reverse Recovery Charge (Qrr), Technology.
CGD65A130S2
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →CGD65A130SH2 Tỷ lệ tối đa & tính chất điện
| Kiểu transitor | GaN HEMT, N-Channel, Enhancement Mode |
| Technology | GaN-on-Si with ICeGaN® gate |
| Drain-Source Voltage (VDS) | 650 V |
| Continuous Drain Current (ID) | 12 A |
| On-Resistance (RDS(on)) | 55 mΩ (typical) |
| Hộp | 16-DFN (8x8 mm) with exposed thermal pad |
| Kiểu lắp đặt | Surface Mount |
| Gate Threshold | ICeGaN® 5 V compatible gate-threshold window |
| Current Sense Pin | Integrated CS output (digital/analog ratio) with NL³ circuit |
| Reverse Recovery Charge (Qrr) | Near zero (GaN intrinsic; datasheet figure) |
| Switching Frequency Suitability | Up to several MHz (typical GaN-HEMT range) |
| Cấp MSL | MSL3 (typical for 16-DFN GaN packages) |
| Trạng thái RoHS | Compliant |
| Đông trùng haogen | Yes |
Cấu hình chân CGD65A130SH2
| Chân 1 | G — Gate input - ICeGaN® compatible, 5 V logic-level drive |
| Chân 2 | S — Source / power ground reference for the gate-drive loop |
| Chân 3 | CS — Integrated current-sense output (ratio to ID, NL³ circuit) |
| Chân 4 | NC — Not connected (per datasheet) |
| Chân 5 | NC — Not connected (per datasheet) |
| Chân 6 | NC — Not connected (per datasheet) |
| Chân 7 | NC — Not connected (per datasheet) |
| Chân 8 | NC — Not connected (per datasheet) |
| Chân 9 | NC — Not connected (per datasheet) |
| Chân 10 | NC — Not connected (per datasheet) |
| Chân 11 | NC — Not connected (per datasheet) |
| Chân 12 | NC — Not connected (per datasheet) |
| Chân 13 | NC — Not connected (per datasheet) |
| Chân 14 | NC — Not connected (per datasheet) |
| Chân 15 | NC — Not connected (per datasheet) |
| Chân 16 | PAD — Drain and thermal pad (bottom exposed pad) |
Ứng dụng tiêu biểu
CGD65A130SH2 phù hợp cho 6 Áp dụngs: USB-PD High-Density Charger, Totem-Pole PFC Front End, Half-Bridge LLC and Quasi-Resonant DC/DC, Photovoltaic Micro-Inverter and Optimiser, Brushless DC and Servo Motor Drive, Server and Telecom Hot-Swap / ORing Switch.
USB-PD High-Density Charger
The CGD65A130SH2 supports 65 W to 240 W USB-PD charger designs by enabling >500 kHz switching where silicon superjunction MOSFETs lose efficiency. Its 650 V rating covers universal input (85-265 VAC) PFC + LLC or QR topologies, the 55 mΩ R_DS(on) keeps conduction loss below 1.5 W at 240 W, and the 5 V gate-threshold ICeGaN® compatibility removes a negative bias supply, shrinking the BOM and the high-side isolator size. The integrated current-sense pin feeds cycle-by-cycle over-current protection without a series shunt, reducing footprint. Pair this part with a TI UCC28640 / NCP1343 controllers for a 100 W reference design.
Được đề xuất
Totem-Pole PFC Front End
For 1-3 kW PFC stages in server, telecom, and 1U rectifier designs, the CGD65A130SH2 provides low-voltage-stress switching at CCM totem-pole where discrete Si MOSFETs suffer excessive body-diode reverse-recovery loss. Per CGD application notes, the device's near-zero Qrr eliminates the dead-time-induced reverse-conduction loss that penalises CCM operation, while the ICeGaN® gate - with a 5 V drive window - allows high-side GaN to be driven from the same supply rail as the controller. The 16-DFN exposed pad dissipates high-side and low-side losses into a 25 x 25 mm top-side copper pour. Reference: 2.5 kW GaN totem-pole PFC design in CGD ICD-1010 application brief.
Được đề xuất
Half-Bridge LLC and Quasi-Resonant DC/DC
The CGD65A130SH2 suits high-frequency LLC, CLLLC, and quasi-resonant DC/DC stages thanks to its low output capacitance (Coss) and 55 mΩ R_DS(on). In a 500 V to 12 V / 48 V LLC brick for telecom, switching at 1-2 MHz with CGD GaN HEMTs reduces transformer size by 4x compared with Si SJ MOSFETs and increases efficiency by ~1.5%. The integrated current-sense pin can be tied to a cycle-by-cycle comparator on the controller, replacing an external current transformer or shunt. Pair this part with TI UCC25640x controllers, Infineon EiceDRIVER™ 2EDi families, or CGD's own EZDrive reference board.
Được đề xuất
Photovoltaic Micro-Inverter and Optimiser
The CGD65A130SH2 fits single-panel PV micro-inverters and DC optimisers where 80 V input from a single PV panel feeds a 400 V DC bus and an isolated DC/DC. The 650 V drain-source rating gives ample de-rating on the 400 V bus (50% de-rated), the 12 A continuous drain current supports ~500 W per micro-inverter channel, and the near-zero Qrr simplifies isolated DCM flyback stages by avoiding reverse-recovery-induced ringing. The exposed-pad 16-DFN allows top-side cooling on a convection-cooled PCB. Pair with TI SM72441 or ON Semi NCP1246 primary controllers with synchronous-rectifier GaN secondary.
Được đề xuất
Brushless DC and Servo Motor Drive
In brushless DC (BLDC) and low-voltage servo drives between 100 V and 600 V bus, the CGD65A130SH2 acts as the high-side/low-side leg in a three-phase inverter. Above 100 kHz PWM, Si MOSFETs see excessive switching loss; the CGD device's 55 mΩ on-resistance plus near-zero reverse-recovery charge enables >2 kW continuous BLDC drives with 96%+ efficiency, even in robots and small EV auxiliaries. The integrated current-sense output can be used both for motor phase-current sensing (eliminating one in-line shunt) and for short-circuit protection - critical for compact robotic drives that require response <1 µs. Reference: CGD AN-0011 motor-drive GaN evaluation board.
Được đề xuất
Server and Telecom Hot-Swap / ORing Switch
In 48 V to 12 V intermediate bus converters and 48 V hot-swap/ORing applications with up to 600 V transient tolerance, the CGD65A130SH2 implements the switching element of a buck or series-element eFuse. CGD documentation positions 650 V GaN HEMTs as a path to higher-power-density bricks in OCP/Open Rack v3 server architectures; near-zero Qrr removes reverse-recovery loss when the eFuse turns on under short-circuit and the integrated current-sense pin yields sub-microsecond OCP response. The 16-DFN (8x8 mm) exposed-pad package supports bottom-side cooling for ORing switches in 1U server power shelves. Reference: OCP ORv3 48 V brick topology using 650 V GaN.
Được đề xuất
Tóm tắt các sản phẩm được đề xuất
Dữ liệu tham khảo kỹ thuật cho CGD65A130SH2 — so sánh, hướng dẫn thiết kế và thông tin tuân thủ.
Hướng dẫn chọn lựa
So sánh với các sản phẩm thay thế
| Tham số | Sản phẩm này | CGD65A130S2 |
|---|---|---|
| Brand | Cambridge GaN Devices | Cambridge GaN Devices |
| Package | 16-DFN (8x8 mm) | 16-DFN (8x8 mm) - same |
| Drain-Source Voltage | 650 V | 650 V |
| Continuous Drain Current | 12 A | 12 A |
| RDS(on) (typical) | 55 mΩ | 55 mΩ |
| Gate Technology | ICeGaN® (5 V compatible) | ICeGaN® (5 V compatible) |
| Current Sense Pin | Yes (integrated + NL³) | No (legacy non-CS variant) |
| Lifecycle | Active | EOL/PCN-flagged (use SH2 instead) |
Bảo phân biệt quan trọng
- Integrated current-sense pin with NL³ circuit on the same 16-DFN footprint (vsCGD65A130S2)
- ICeGaN® gate enables 5 V standard-MOSFET-driver compatibility (vsGeneric 650 V GaN HEMT competitors)
Ghi chú thiết kế
Estimated: with R_DS(on) of 55 mΩ and 12 A continuous drain current, conduction loss at full load is approximately 12^2 x 0.055 ≈ 7.9 W. The exposed-pad 16-DFN requires a top-side copper thermal island of at least 600 mm² (or a 6 cm² inner-plane coverage) and a 5 x 5 thermal-via array (0.3 mm hole, 0.6 mm pitch) directly under the exposed pad to keep junction temperature rise below 60°C in a 25°C ambient. Without this, the device will thermal-limit well below 12 A.
The ICeGaN® gate technology is 5 V compatible, but never drive the gate hard beyond the absolute maximum V_GS specified in the datasheet. Over-driving wastes power and accelerates gate oxide ageing; under-driving causes R_DS(on) to rise sharply at the Miller plateau. Place a 10 nF ceramic gate-source resistor loop as close as possible to pins 1 and 2 to suppress common-mode ringing at >500 kHz switching - high dV/dt noise on the source-node returns can couple back into the gate loop and cause shoot-through in a half-bridge.
Keep the gate-driver loop area below 5 mm² (gate-source capacitor return path inside the gate-driver and between CGD65A130SH2 pins 1-2). For totem-pole PFC or half-bridge LLC, the high-side and low-side source returns must be Kelvin-connected to the gate-driver's COM/GND pin, NOT shared with the main power-ground return. This separation removes the miller-effect-induced false trigger caused by di/dt on the shared inductance. Reference: CGD AN-0011 totem-pole layout guidelines.
Thông tin tuân thủ
RoHS compliant per CGD product page. AEC-Q100 not applicable (consumer/industrial GaN HEMT). Conflict-mineral and REACH compliance status not explicitly listed in verified web data; confirm with CGD for production-volume orders.
